JPH0262838U - - Google Patents
Info
- Publication number
- JPH0262838U JPH0262838U JP14172388U JP14172388U JPH0262838U JP H0262838 U JPH0262838 U JP H0262838U JP 14172388 U JP14172388 U JP 14172388U JP 14172388 U JP14172388 U JP 14172388U JP H0262838 U JPH0262838 U JP H0262838U
- Authority
- JP
- Japan
- Prior art keywords
- operational amplifier
- feedback
- output signal
- sample
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Description
第１図は本考案になる帰還型雑音抑圧回路を備
えた１ビツトＡ／Ｄ変換器の一実施例を示す回路
図、第２図は従来例を示す回路図である。
１……第１のオペアンプ、２……第２のオペア
ンプ、３……２値量子化回路、４……遅延回路、
Ｒ１，Ｒ２……入力抵抗、Ｒ３，Ｒ４……帰還抵
抗。
FIG. 1 is a circuit diagram showing an embodiment of a 1-bit A/D converter equipped with a feedback type noise suppression circuit according to the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1... First operational amplifier, 2... Second operational amplifier, 3... Binary quantization circuit, 4... Delay circuit,
R1 , R2 ...Input resistance, R3 , R4 ...Feedback resistance.
Claims (1)
れた出力信号とが差分入力され、第１のキヤパシ
タによる負帰還がなされた第１のオペアンプと、
この第１のオペアンプの出力と前記１サンプル遅
延して帰還された出力信号とが和入力され、第２
のキヤパシタによる負帰還がなされた第２のオペ
アンプと、この第２のオペアンプの出力が入力さ
れてデジタル出力信号を出力する２値量子化回路
と、前記デジタル出力信号を１サンプル遅延させ
て、前記第１及び第２のオペアンプへ出力する遅
延回路とからなる１ビツトＡ／Ｄ変換器であつて
、 前記第１のオペアンプへ入力されるアナログ入
力信号と遅延帰還量との帰還比と、前記第２のオ
ペアンプへ入力される第１のオペアンプの出力と
遅延帰還量との帰還比とを一致させたことを特徴
とする帰還型雑音抑圧回路を備えた１ビツトＡ／
Ｄ変換器。[Claims for Utility Model Registration] A first operational amplifier to which an analog input signal and an output signal delayed by one sample and fed back are differentially input, and negative feedback is performed by a first capacitor;
The output of the first operational amplifier and the output signal delayed by one sample and fed back are sum-inputted, and the second operational amplifier is inputted as a sum.
a second operational amplifier that is subjected to negative feedback by a capacitor; a binary quantization circuit that receives the output of the second operational amplifier and outputs a digital output signal; and a binary quantization circuit that delays the digital output signal by one sample, and A 1-bit A/D converter comprising a delay circuit outputting to a first and a second operational amplifier, the feedback ratio between an analog input signal input to the first operational amplifier and a delay feedback amount, A 1-bit A/2 amplifier equipped with a feedback noise suppression circuit characterized in that the feedback ratio between the output of the first operational amplifier input to the second operational amplifier and the amount of delayed feedback is matched.
D converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14172388U JPH0262838U (en) | 1988-10-28 | 1988-10-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14172388U JPH0262838U (en) | 1988-10-28 | 1988-10-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0262838U true JPH0262838U (en) | 1990-05-10 |
Family
ID=31407046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14172388U Pending JPH0262838U (en) | 1988-10-28 | 1988-10-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0262838U (en) |
-
1988
- 1988-10-28 JP JP14172388U patent/JPH0262838U/ja active Pending
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