JPH0262920B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit, and particularly to a memory circuit configured with an insulated gate field effect transistor (MISFET).

In a static RAM (random access memory), a write circuit and a read circuit can be used for multiple digit lines by connecting the digit line to a common data line via a switch means (column gate) controlled by the output of a Y decoder. can be shared, and the circuit can be simplified. In this RAM, a memory cell selected by an output of an X decoder and an output of a Y decoder among a plurality of memory cells is connected to a common data line via a digit line and a switch means. Information is written into the selected memory cell via the common data line, or information from the selected memory cell is read via the common data line.

In a memory circuit, peripheral circuits such as a decoder and an input/output circuit require a relatively high lower limit value of the power supply voltage with respect to the memory cells constituting the memory circuit. Under reduced power supply voltage, peripheral circuits may malfunction, and information held in memory cells may be destroyed due to erroneous control signals and data signals.

Access times for memory circuits are limited by operational delays of data transfer means such as switch means.

The static type memory is disclosed in Japanese Patent Application Laid-Open No. 1983-
This is shown in Publication No. 14586.

One object of the present invention is to provide a memory circuit with short access time.

Another object of the present invention is to provide a memory circuit in which the signal level on a common data line changes rapidly.

Another object of the present invention is to provide a memory circuit that can quickly start data transfer.

Another object of the invention is to provide a memory circuit having load means suitable for adding to a digit line.

Another object of the present invention is to provide a memory circuit that operates well even with a reduced power supply voltage.

Another object of the present invention is to provide a memory circuit configured to inhibit the operation of peripheral circuits at a further reduced power supply voltage.

Another object of the present invention is to provide a memory circuit having a power supply voltage detection circuit suitable for controlling the load or peripheral circuit described above.

Further objects of the invention will become apparent from the following description and drawings.

According to one embodiment of the present invention, a load means for a selected memory cell is connected between a digit line and a power supply, and a switch means consisting of a MISFET controlled by the output of a Y-decoder is provided. Connected between the digit line and the power supply.

The switch means does not turn on unless the output level of the Y decoder increases by at least the threshold voltage of the switch means. As a result, the transfer of data via the above switching means is
It does not start during the period from when the Y decoder starts operating until its output level reaches a predetermined value. According to one embodiment of the invention, the high level of the digit line is reduced. The high level of the digit line is connected to multiple enhancements connected in series with the load means connected to this digit line.
It can be reduced by configuring it with MISFETs or by substantially lowering the power supply voltage. Due to the drop in the high level of the digit line, the switching means between the digit line and the common data line is turned on even by a relatively small output level of the Y decoder. As a result, data transfer becomes faster. By lowering the level of the common data line, the readout circuit that receives the signal on the common data line operates with actual sensitivity.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 shows a block diagram of a memory circuit according to an embodiment.

In FIG. 1, 3 is a memory matrix, which includes a plurality of memory cells MS ₁₁ arranged in rows and columns.
to MS _no , word lines W ₁ to W _n , and paired digit lines D1 ₁ , D1 ₀ to D, respectively.
1 _o and D0 _o .

Each memory cell has a selection terminal and a pair of input/output terminals, and MISFETQ ₁ , which constitutes a flip-flop, as shown in the representative MS ₁₁ ,
It consists of Q ₂ , its load resistances R ₁ and R ₂ , and MISFETs Q ₃ and Q ₄ that constitute transmission gates.

The selection terminals of the memory cells arranged in the same row, e.g. MS ₁₁ to MS _1o , are commonly connected to the word line corresponding to that row, e.g. W ₁ , and the selection terminals of the memory cells arranged in the same column, e.g. MS ₁₁ to MS _n1
The input/output terminals of each column are commonly connected to the digit lines corresponding to the column, for example, D1 ₁ and D0 ₁ .

Load means R ₁₁ , R ₀₁ , R _1o , and R _0o are connected between each digit line and the power supply terminal V _CC , respectively. Loading means for this digit line is used for reading information from the memory cells as will be described later. Load resistance of each memory cell R ₁ , R ₂
The digit line has a high resistance in order to reduce the power consumption of the memory cell during a holding operation, whereas the load means for the digit line has a relatively low resistance for a read operation.

Each of the above digit lines is also connected to a column input/output circuit 4.

The column input/output circuit 4 is provided between each digit line pair and the common data lines CD ₁ and CD ₀ as shown in the figure, and includes MISFETs Q ₅ to Q ₈ as transmission gates controlled by the Y decoder 3. I'm here.

X decoder ₁ has address input terminals
Address buffers BX ₁ to BX _i respectively from X _i
receives an address signal via the address signal, selects one of the word lines _W1 to _Wn in accordance with the address signal, and sets the signal level of the selected word line to high level. Note that unselected word lines are at a low level.

Like the X decoder, Y decoder 3 also receives address signals from address input terminals Y ₁ to Y _k via address buffers BY ₁ to BY _k , respectively, and selects one of digit selection lines C ₁ to C _o . Select and set the signal level to high.

The transmission gate MISFET of the memory cell in the row selected by the X-decoder 1 is turned on, and the flip-flops of the memory cell are connected to their corresponding digit lines via the transmission gate MISFET.

The digit line of the column selected by the Y decoder 3 is connected to the common data line via the column input/output circuit 4. As a result, the memory cells selected by X decoder 1 and Y decoder 3 are connected to the common data line.

In the selected row, the memory cell
The MISFETs Q ₁ and Q ₂ serve as a load to the load means connected to the digit line, and the potential of the pair of digit lines is determined by the information stored in this memory cell. The potential of the common data line is determined by the potential of the selected digit line. The potential of the common data line, that is, the stored information of the selected memory cell is read out by the readout circuit 6.

For example, the common data line is
When CD ₁ is made high and CD ₀ is made low, the selected memory cell, e.g. MS ₁₁
MISFET Q ₁ is turned off by the low level of this common data line CD ₀ , and Q ₂ is turned on by the off state of Q ₁ . That is, information is written into the selected memory cell.

In this embodiment, although not particularly limited, the output terminal of the read circuit 6 and the output terminal of the write circuit 5 are commonly connected to the input/output terminal I0.

The above write circuit 5 is controlled by a write control circuit 7 which receives a chip selection signal and a write control signal, and the read circuit 6 is controlled by a read control circuit 8 which receives similar signals.

The memory circuit of FIG. 1 is in a standby state when the chip selection signal is at a low level, and is in a selected state when it is at a high level. Also, when selecting a step, the write control signal
A low level of WE causes a write state, and a high level causes a read state.

FIG. 4 shows an example of a timing chart of the memory circuit shown in FIG. Note that in the same figure, the solid line indicates the case of a write operation, and the broken line indicates the case of a read operation.

In a write operation, the X address input terminal
X ₁ to X _i and Y address input terminal Y ₁ to
The address input applied to Y _k is updated at time t0. Although it is not necessarily the same time as the above time, the high level of the write control signal is changed to a low level.

The chip selection signal, which was at a high level when no chip was selected, is set to a low level at time t1.
When the chip selection signal and the write control signal become low level, the write control circuit 7
The output signal 1 changes from high level to low level at a slightly delayed time t3. Above output signal
When WE1 becomes low level, the write circuit 5 starts operating.

At time t5, the chip selection signal returns from a low level to a high level, so that the output signal 1 of the write control circuit 7 returns from a low level to a high level at time t7.

At time t10, the write control signal is returned from low level to high level again. Note that the output signal IOC of the read control circuit 8 is maintained at a high level as shown in FIG. 4 due to the low level of the write control signal.

The low level of the chip select signal and the high level of the write control signal cause the memory circuit to perform a read operation.

As the chip selection signal becomes low level at time t1, the output signal IOC of the readout control circuit 8 changes from high level to low level at time t4, and as a result, the readout circuit 6 starts operating.

The chip selection signal returns to high level at time t5, causing the output signal to change at time t9.
IOC returns to high level and the read circuit 6 stops operating.

Although the write control circuit 7 and the read circuit 8 are not particularly limited, their specific circuits are as shown in FIG.

The write control circuit 7 is MISFETQ ₆₁ or
NOR gate circuit configured by Q ₆₃ and MISFETQ ₆₄ and Q ₆₅ , Q ₆₆ and Q ₆₇ , Q ₆₈ and Q ₆₉ respectively
It consists of three inverter circuits. The write circuit 5 is controlled by the outputs 1 and 2, and the circuit 10 described later is controlled by the output WE3.

Each of the readout control circuits 8
MISFETQ ₇₀ and Q ₇₁ , Q ₇₂ and Q ₇₃ , Q ₇₄ and Q ₇₅ , Q ₇₉ and
It consists of four inverter circuits made up of _Q80 and a NOR gate circuit made up of _MISFETQ76 to _Q78 . The readout circuit 6 is controlled by the output IOC.

Note that MISFETs such as Q ₆₁ and Q ₆₄ are depletion type and can be distinguished from enhancement type MISFETs such as Q ₆₂ and Q ₆₃ by the dashed line between the source and drain as shown in the figure. ing.

Figure 2 shows the digit line in the circuit of Figure 1.
A specific circuit example of the load means _R11 connected to _D11 is shown. Other load means R ₀₁ and the like have the same configuration as R ₁₁ .

The load means R ₁₁ is a depletion type MISFET Q ₉ whose gate and source are shorted as shown in the figure.
It consists of a series connection of enhancement type MISFET Q ₁₀ and Q ₁₁ with gate and drain shorted.
_This load means has two enhancement-type
A voltage drop of 2V _th is generated, which is determined by the threshold voltage V _th of MISFETQ ₁₀ and Q ₁₁ . Therefore, the high level of the signal on the digit line _D11 is suppressed to _Vcc - _2Vth (where _Vcc is the power supply voltage). depression type
_MISFETQ9 operates as a current limiting element and is used to limit the current flowing from load means _R11 to digit line _D11 when writing information to the memory cell.

FIG. 6 shows a specific circuit example of the Y decoder 3 shown in FIG. This Y decoder 3 consists of a plurality of NOR gate circuits. The NOR gate circuit with output line Y ₁ has a depletion load MISFETQ ₅₅
and enhancement type MISFETQ ₅₆ or Q ₅₇ for input. For input
The gates of MISFETQ ₅₆ and Q ₅₇ are provided with input signals from a plurality of address buffers each outputting a non-inverted signal a ₀ and an inverted signal ₀ in response to an address input A _i as shown in detail in FIG. Outputs are appropriately selected and added. If at least one of the gate inputs of MISFETQ ₅₆ to Q ₅₇ is at a high level, a non-selection level, that is, a low level signal is output to the output line _Y1 . When all of the input gates are at low level, a selection level, that is, a high level signal is output to the output line _Y1 . depression load
MISFETQ ₅₅ does not have a voltage drop due to threshold voltage as in enhancement MISFET, so the high level of the Y-decoder output signal is
It reaches almost the power supply voltage _Vcc .

FIG. 8 shows circuits 10 and 11, which will be described later.
A specific circuit of a write circuit 5 and a read circuit 6 is shown.

The write circuits 5 each include MISFETQ ₉₅ and
Three inverter circuits consisting of Q ₉₆ , Q ₉₇ and Q ₉₈ , Q ₉₉ and Q ₁₀₀ , each with MISFETQ ₁₀₁
2 consisting of Q ₁₀₄ and Q ₁₀₇ to Q ₁₁₀
NOR gate circuits, each with
It consists of two push-pull output circuits consisting of MISFETQ ₁₀₅ , Q ₁₀₆ , Q ₁₁₁ and Q ₁₁₂ . The gate of MISFETQ ₉₆ in this circuit 5 is the input/output terminal I0
The gates of Q ₁₀₂ and Q ₁₀₈ are connected to the output line 1 of the write control circuit 7 _in FIG.
The gate of Q ₁₁₀ is connected to the output line 2 of the circuit 7 above. Push-pull output circuit
The source of MISFETQ ₁₀₅ and the drain of Q ₁₀₆ are connected to the common data line CD ₀ , and the source of Q ₁₁₁ and the drain of Q ₁₁₂ are connected to the common data line CD ₁ .

With the circuit configuration shown in Figure 5, the above output line 1 and
The signal level of WE2 is low only during the chip selection period for writing, that is, during the period when both the chip selection signal and the write control signal are at low level. During this period
Due to the OFF state of MISFETQ ₁₀₂ , Q ₁₀₃ , Q ₁₀₈ , and Q ₁₁₀ , signals with opposite phases appear at the output terminals of the above two NOR gate circuits according to the signal level of the input/output terminal I0, and these two NOR gate circuits In response to the outputs of the two push-pull output circuits, signals having phases opposite to each other appear at the output terminals of the two push-pull output circuits. That is, if the signal at the input/output terminal I0 is at a high level, one push-pull output circuit outputs the common data line CD ₁
is set to a high level, and the other push-pull output circuit sets the common data line CD ₀ to a low level. Terminal I0
On the other hand, if the signal is low level, the common data line CD ₁
is a low level and CD ₀ is a high level.

During the chip selection period for reading and the chip non-selection period, the signal levels of the output lines WE1 and WE2 are high, and the output signals of the two NOR gate circuits are connected to the input/output terminal I0.
The signal level remains low regardless of the signal level. During this period, MISFETQ ₁₀₅ , Q ₁₀₆ , Q ₁₁₁ , and Q ₁₁₂ of the two push-pull output circuits are all in the off state, so that the output is floating.

The readout circuit 6 includes a first stage differential circuit composed of MISFETQ ₁₁₃ to Q ₁₂₁ , and a first stage differential circuit composed of MISFETQ 113 to Q ₁₂₁ , and
The second stage differential circuit composed of Q ₁₂₅ and the above 2
A third-stage differential circuit with the same configuration as the first-stage differential circuit, a NOR gate circuit each composed of Q ₁₂₆ to Q ₁₂₈ and Q ₁₂₉ to Q ₁₃₁ , and a push-pull output circuit composed of Q ₁₃₂ and Q ₁₃₃ . It consists of
Note that in the first stage differential circuit, Q ₁₂₀ whose gate receives a bias via Q ₁₂₁ serves as a source load for Q ₁₁₈ and Q ₁₁₉ . Q ₁₁₇ produces a drain current that is dependent on the source output of Q ₁₁₈ and Q ₁₁₉ . Q ₁₁₇ or
Due to the negative feedback operation by the _Q121 circuit, the output level of the first stage differential circuit is controlled to be almost constant.

With the configuration shown in FIG. 5, the output line IOC is at a low level during the chip selection period for reading. During this period, MISFETs Q ₁₂₈ and Q ₁₃₁ in FIG. 8 are turned off, and the output terminals of the two NOR gate circuits in the circuit 6 receive signals in opposite phases to each other according to the levels of the common data lines CD ₁ and CD ₀ . A signal appears in the push-pull circuit in response to the output of this NOR gate circuit. i.e. common data line CD ₁
If CD 0 is high level and CD ₀ is low level, the output circuit consisting of Q ₁₃₂ and Q ₁₃₃ outputs high level. Conversely, if the common data line CD ₁ is at a low level and the common data line CD ₀ is at a low level, a low level is output.

During the chip selection period for writing and the chip non-selection period, the signal on the output line IOC becomes high level, and MISFETQ ₁₂₈ and Q ₁₃₁ are turned on. Therefore, the outputs of the two NOR gate circuits in the circuit 6 are at a low level regardless of the signal levels of the common data lines CD ₁ and CD ₀ . The push-pull output circuit makes the output floating by turning off the two MISFETs Q ₁₃₂ and Q ₁₃₃ at the same time.

In this embodiment, by configuring the load means connected to the digit line as shown in FIG. 2 above, the information stored in the memory cells can be read out at high speed, as will be explained next. .

The memory cell has its transmission gate MISFETQ ₃ ,
When Q ₄ is in the off state, the internal high load resistors R ₁ , R ₂
Information is stored by MISFETQ ₁ and Q ₂ . The stored information "1" corresponds to, for example, MISFET _{Q 1} being off and Q ₂ being on, and conversely, "0" corresponding to MISFET Q ₁ being on and Q ₂ being on.
is in the off state.

The circuit operation when the memory cell MS ₁₁ is selected and the stored information is read out is as follows.
It is assumed that the memory cell MS ₁₁ stores "1" in advance. The common data line also has a high level according to its previous state due to its stray capacitance (not shown).
It is assumed that the

When the word line _W1 becomes high level by the X decoder, the memory cells _MS11 to _MS1o in the first row
is selected, and its transmission gates MISFETQ ₃ and Q ₄ are turned on.

Due to the ON state _of MISFETQ ₃ and Q ₄ mentioned above _, load means R ₁₁ and R ₀₁ having relatively high resistance values connected to digit lines _{D1 1 and} D0 ₁ serve as a load for MISFETQ 1 and Q 2 of memory cell MS 11. . Since MISFET Q ₁ is in the off state according to the previously stored information, no current flows through the load means R ₁₁ , and this load means only experiences a voltage drop of approximately 2V _th as described above. As a result, the digit line _D11 becomes at a high level of _Vcc - _2Vth . On the other hand, since MISFETQ ₂ is in the on state, current flows through the load means R ₀₁ , which causes _a relatively large voltage drop. As a result, the digit line _D01 becomes low level.

In the Y decoder 3, the MISFETs _{Q 5} and Q ₆ of the column input/output circuit 4 are turned on due to the high level of the output line C ₁ , and the levels of the digit lines D1 ₁ and D0 ₁ are set to the common data lines CD ₁ and CD ₀ , respectively. be transferred.

FIG. 9A shows the selected output line of Y decoder 3.
It shows the relationship between the signal change curve at _C1 , the signal level _DH2 at the digit line _D11 , and the signal level _DL2 at the digit line _D01 . Note that the output signal of the Y decoder 3 changes at the same time as the output signal of the X decoder 1 or slightly earlier due to the circuit configuration. Therefore, the signal levels of the digit lines D1 ₁ and D0 ₁ are not necessarily fixed at the start of the operation of the Y decoder 3.For ease of understanding and convenience of explanation, the signal levels of the digit lines are shown as fixed levels in FIG. 9A. It is shown as

As shown in FIG. 9A, the signal on the selected output line _C1 of the Y decoder 3 (hereinafter referred to as signal _C1 )
begins to rise from a low level at time t20.

At time t21, the level of signal _C1 reaches the low level _DL2 of digit line _D01 .

At time t22, the level of signal _C1 becomes higher than the level _DL2 of digit line _D01 by a threshold voltage. Therefore, the column input/output circuit 4
MISFETQ ₆ starts conducting. In this case, since the digit line _D01 is at a low level and the common data line is at a high level, the electrode P on the digit line side of MISFET _Q6 acts as a source, and the electrode _P2 on the common data line side acts as a drain. The level of the common data line CD ₀ , which was at a high level due to the load means RC ₀ and stray capacitance (not shown), is as follows.
With the start of conduction of MISFET _Q6 , the voltage begins to drop to the level of the digit line _D01 as shown by the curve _CL2 in FIG. 9B. Note that the rate at which the level of the common data line CD ₀ falls is determined by the stray capacitance of the common data line CD ₀ and the digit line D0 ₁ and the on-resistance of the MISFET Q ₆ .

The signal _C1 reaches the level of the high level digit line _D11 at time t24, and becomes higher than the level of the digit line _D11 by the threshold voltage _Vth at time t25. As a result, MISFETQ ₅ starts conducting. The level of the common data line CD ₁ changes as shown by the curve CH ₂ in FIG. 9B.

The read circuit 6 responds to the above level difference between the common data lines CD ₁ and CD ₀ . The source of MISFETQ ₁₁₃ in the first stage differential circuit of readout circuit 6
The curve shown in Figure 9 C is at the node P ₅ with the drain of Q ₁₁₄ .
A signal like _P52 whose level is determined approximately at time t23 appears.

If the enhancement type MISFETQ ₁₁ is removed from the load means connected to the digit line as shown in Figure 2, the high level of the digit line _D11 when reading information will change from the level _DH2 of Figure 9A.
Level DH ₁ higher by threshold voltage of MISFETQ ₁₁
Changes to MISFETQ ₂ in the on state of the memory cell,
Due to the conductance of Q ₄ and the conductance of the load means, the low level of digit line D0 ₁ increases from level DL ₂ of FIG. 9A to DL ₁ .

Due to the above-mentioned level increase, the level of the signal C ₁ that turns on MISFETs _{Q 5} and Q ₆ increases, and as a result, the level change of the common data line CD ₀ is delayed as shown by the broken line CL ₁ in FIG. 9B. Also common data line
The level change of CD ₁ is also delayed as indicated by the broken line CH ₁ in FIG.

The level of the node _P5 of the readout circuit is as indicated by the broken line _P51 in FIG. 9C.

In this embodiment, by lowering the level of _the digit line using a load means as shown _{in FIG} . state and the difference between the level of the digit line and the level of signal _C1 becomes large.
Since the voltage between the source and gate of MISFETQ ₅ and Q ₆ increases and the conductance between the source and drain increases, data transfer between the digit line and the common data line is performed at high speed.

FIG. 11 shows the input voltage V _I versus output voltage V ₀ characteristic of an inverter circuit consisting of a drive MISFET and a load MISFET connected to its drain.
The steeper the slope of the characteristic curve, the greater the gain of the circuit. In the MIS inverter circuit, the input signal becomes larger as it approaches the threshold voltage V _th of the drive transistor.

In this embodiment, common data lines CD ₁ ,
The level of CD ₀ has been reduced by the digit line load and the readout circuit will operate at high gain.

As a result, according to this embodiment, the readout circuit also operates at high speed.

12 to 15 show modifications to the loading means of FIG. 2. In Figure 12, the second
MISFETQ ₁₃₅ which corresponds to MISFETQ ₉ in the figure and
MISFETQ ₁₃₄ , which corresponds to MISFETQ ₁₀ , has been replaced. In Figure 13, MISFETQ ₁₃₇ and
By means of a voltage divider circuit composed of Q ₁₃₈ and
The voltage applied from the source of MISFETQ ₁₃₉ to digit line _D11 is lowered. 14th
In the figure, MISFETQ ₁₄₁ is controlled by a write control signal. This loading means is
During read operation, is high level and 2V _th
This results in a voltage drop of .

In Figure 15, MISFETQ ₉ to Q ₁₁ in Figure 2
A series circuit consisting of MISFETQ ₁₄₂ to Q ₁₄₄ similar to the above and a series circuit consisting of MISFETQ ₁₄₅ and Q ₁₄₆ are connected in parallel. In this circuit of Fig. 15,
MISFETQ ₁₄₆ is connected to power supply voltage detection circuit 9, which will be described later.
Controlled by a similar circuit. When the power supply voltage falls below the detection voltage of the power supply voltage detection circuit, the high level detection signal from this power supply voltage detection circuit is
Added to the gate of MISFETQ ₁₄₆ . In the circuit of Fig. 15, when the power supply voltage is greater than the above detection level by controlling a switch such as MISFETQ ₁₄₆ , a voltage drop of 2V _th is caused by MISFETQ ₁₄₂ or Q ₁₄₄ , and the power supply voltage is lower than the above detection level. If small, MISFETQ ₁₄₆ will cause a voltage drop of V _th to occur. In the circuit shown in Figure 15, MISFETQ ₁₄₆
is controlled by a switch so that the high level on the digit line increases when the supply voltage drops.
As a result, the read circuit 6 receives a substantially constant voltage regardless of the power supply voltage. Therefore, when the load means of FIG. 15 is used, the circuit can operate satisfactorily even at a relatively low power supply voltage.

According to this embodiment, common data lines CD ₁ ,
CD ₀ is set to the same potential when no chip is selected by the load means RC ₁ and RC ₀ and the switch circuit 11 controlled by the pulse generating circuit 10 that operates when the chip selection is completed, and the high level of the digit line is set to the same potential when the chip is not selected. be brought to the same level as As a result, the access time of the memory circuit when the chip is again in the selected state is shortened. In contrast, the common data lines CD ₁ , CD ₀
If the load means RC ₁ , RC ₀ and the circuit as described above are not connected to the chip, when the chip is not selected, one of the common data lines will maintain the stray capacitance at the high level determined during the previous chip selection, and the other will maintain the low level. Hold the level. When the chip is selected again and the stored information of the memory cell is read out, when this stored information has a value that reverses the level of the common data line, the one common data line changes from high level to low level, The other common data line changes from low level to high level. As a result, it takes a relatively long time for the potential difference between the pair of common data lines to reach a sufficient potential difference required by the readout circuit.

The load means RC ₁ and RC ₀ have the same configuration,
The specific circuit for RC ₁ is shown in Figure 3. This load means _RC1 has a similar construction to the load means shown in FIG. 2 which is connected to the digit line.

The specific circuits of the pulse generation circuit 10 and the switch circuit 11 are shown in FIG. 8 mentioned above.

Each pulse generation circuit 10 is MISFETQ ₈₁
It consists of two inverter circuits made up of _Q82 , _Q83 and _Q84 , a Schmitt circuit made up of _Q85 to _Q88 , and a two-input NOR gate circuit made up of _Q89 to _Q90 . The output signal WE3 from the write control circuit 7 in FIG. 5 is applied to one of the NOR gate circuits with a delay via the two inverter circuits and the Schmitt circuit, and the output signal WE3 is applied to the other input terminal. Added directly.

With the circuit configuration shown in FIG. 5, the signal WE3 is
It is at a high level during a write operation, and is at a low level when a chip is not selected and during a read operation. signal
When WE3 is at a low level, the gate input of MISFETQ ₈₉ is at a high level, so the output WR of the circuit 10 is at a low level. Similarly, when WE3 is at a high level, the gate input of MISFETQ ₉₁ is at a high level, so the output WR is also at a low level.

The output WR of the circuit 10 changes from MISFETQ 81 to _{Q 88 after the signal WE3 changes from high level to low level and MISFETQ 91 turns} off.
Due to the delay in the circuit, the gate input of _Q89 becomes high level and becomes high level during the period until _Q89 turns on. WE3 and WR are shown in FIG. 4 above.

The switch circuit 11 includes a MISFETQ ₉₂ connected between the power supply _Vcc and one common data line _CD1 ,
It consists of a MISFETQ ₉₃ connected between the power supply V _cc and the other common data line, and a MISFETQ ₉₄ connected between the common data lines. these
MISFETQ ₉₂ to Q ₉₄ are turned on by the high level of the output WR of the pulse generating circuit 10.

FIG. 10A reproduces the signal WR shown in FIG. 4, and FIG. 10B shows potential changes on a pair of common data lines. During the chip selection period before time t8, the signal CH 2 on one common data line, for example CD _1, is at a high level, and the signal CH ₂ on the other common data line, for example CD ₀ , is at a high level.
The signal CL ₂ has become low level.

At time t8, switch circuit 1 is activated by signal WR.
Each MISFET of 1 begins to conduct. MISFETQ ₉₂ ,
Q ₉₃ acts to raise the potential of the common data lines CD ₁ and CD ₀ to the power supply V _cc , respectively.
MISFETQ ₉₄ acts to make the mutual potential difference between common data lines CD ₁ and CD ₀ zero. The rate of change of the potential of the common data line is MISFETQ ₉₂ or
Limited by the conductance of _Q94 and the stray capacitance of the common data line.

By appropriately providing each MISFET in the pulse generating circuit 10, the time _t8 to _t9 at which the signal WR becomes high level is set. As a result, the common data line CD ₁ and
The potential of CD ₀ is raised to approximately the potential determined by the load means RC ₁ and RC ₀ as shown in FIG. 10B. At times after time t9 when MISFETQ ₉₂ to Q ₉₄ turn off, the common data lines CD ₁ ,
The potential of CD ₀ is maintained by load means RC ₁ , RC ₀ .

Note that when the chip non-selection period is relatively long, the potentials of the common data lines CD ₁ and CD ₀ are the same as that of the load means RC ₁ ,
Since it also increases due to RC ₀ , switch circuit 11
MISFETQ ₉₂ between power supply V _cc and common data line
It is also possible to remove and Q ₉₃ . However, the load means RC ₁ , RC ₀ act as a load for the selected memory cell during the read period;
Conductance is limited. MISFETQ ₉₂ and
By providing Q ₉₃ , the common data line CD ₁ ,
CD ₀ can be brought to the same potential and the same potential as the high level of the digit line in a relatively short time, and the memory circuit can operate satisfactorily even when the chip non-selection period is short.

According to this embodiment, the memory cell continues its storage operation even under a lower power supply voltage, and the information stored in the memory cell is prevented from being destroyed.

The specific circuit of the X decoder 1 in FIG.
It is configured as shown in the figure.

The circuit for selecting the word line _W1 of the X decoder 1 is MISFETQ ₃₉ to
A NOR gate circuit composed of Q ₄₁ ,
It consists of an inverter circuit made up of MISFETQ ₄₂ and Q ₄₃ , and a push-pull output circuit made up of MISFETQ ₄₄ and Q ₄₅ .

MISFETQ ₄₀ or Q ₄₁ of the above NOR gate circuit
To the gate of , symbols from a plurality of address buffer circuits as shown in FIG. 7 are appropriately selected and applied.

When selecting word line W ₁ , the above
All gate inputs of MISFETQ ₄₀ or Q ₄₁ are low level, and the NOR gate circuit outputs a high level signal. As a result, a high level signal is output from the push-pull output circuit consisting of _Q44 and _Q45 .

Conversely, if word line W ₁ is not selected,
At least one of the gate inputs of MISFETQ ₄₀ to Q ₄₁ becomes high level, and the NOR gate circuit outputs a low level signal.

When the power supply voltage _Vcc decreases, the level of the high level signal of the address buffer decreases. Power-supply voltage
If the drop in _Vcc is large, the high level signal of the address buffer will no longer be considered high level by the NOR gate circuit of the X decoder. As a result, the NOR gate circuit outputs a high level signal even though it is not selected, and the push-pull output circuit causes the corresponding word line to go high.

When the transmission gate MISFETs of a plurality of memory cells connected to the same digit line are turned on, the flip-flops of the memory cells are undesirably coupled to each other via the digit line. If the memory cells connected to each other have different storage information, one memory cell will destroy the storage information of the other memory cell.

In this embodiment, the NOR gate circuit of X decoder 1 is provided with additional input terminals.
MISFETQ ₅₃ and Q ₅₄ are respectively provided.
These MISFETs Q ₅₃ to Q ₅₄ are turned on when the power supply voltage V _cc decreases by a relatively large amount according to the output of the power supply voltage detection circuit 9 .

As a result, the push-pull output circuit corresponding to each word line outputs a low-level signal when the power supply voltage drops relatively significantly, and the above-mentioned destruction of the information stored in the memory cell is prevented.

As shown in FIG. 16, the power supply voltage circuit 9 includes a first voltage dividing circuit consisting of depletion MISFETQ ₂₅ and Q ₂₆ , a second voltage dividing circuit consisting of enhancement MISFETQ ₂₇ and depletion MISFETQ ₂₈ , and MISFETQ ₂₉ to Q ₃₂ . a first differential circuit having the same configuration as the first differential circuit;
third differential circuits B ₁ and B ₂ and Q ₃₃ and Q ₃₄ respectively;
It consists of first and second inverter circuits made up of _Q35 and _Q36 , and a push-pull output circuit made up of _Q37 and _Q38 .

The first voltage divider circuit consists of depletion MISFETs Q ₂₅ and Q ₂₆ with their gates and sources shorted, respectively.
Therefore, the divided voltage output A has a value proportional to the mutual conductance ratio and the power supply voltage _Vcc .
On the other hand, the second voltage divider circuit consists of an enhancement MISFETQ ₂₇ with its gate and drain shorted and a MISFETQ ₂₈ with its gate and source shorted, so its divided voltage output B is equal to the threshold value of Q ₂₇ . The value is proportional to the ratio of mutual conductance at a power supply voltage equal to or higher than the voltage V _th and the power supply voltage V _cc .

By appropriately designing MISFETs Q ₂₅ and Q ₂₆ and Q ₂₇ and Q ₂₈ , output B can be made larger than output A at a voltage higher than a predetermined power supply voltage, as shown in FIG. Output A can be made larger than output B in the following.

In the voltage detection circuit 9 of FIG. 16, the power supply voltage
When V _cc is higher than the above specified voltage, the outputs of inverter circuits Q ₃₃ and Q ₃₄ are at high level, and the inverter circuit
Since the outputs of Q ₃₅ and Q ₃₆ are at low level, the outputs of push-pull output circuits Q ₃₇ and Q ₃₈ are at low level as shown by curve C in FIG. 17. On the other hand, when the power supply voltage V _cc becomes equal to or less than the above-mentioned predetermined voltage, the output of the above-mentioned output circuit becomes high level. As the supply voltage V _cc decreases further, its output decreases with the supply voltage V _cc . The MISFETs Q ₅₃ to Q ₅₄ are turned on by an output equal to or higher than the threshold voltage V _thL .

In the power supply voltage detection circuit shown in FIG. 16, the voltage difference between the two voltage divider circuits can be arbitrarily changed by the mutual conductance ratio of the MISFETs. Also, by creating a differential voltage
Amplification circuits such as MISFETQ ₂₉ to Q ₃₂ can be used and are therefore highly sensitive.

The invention is not limited to the examples. For example, a load means as shown in FIG. 15 is used as the load means connected to the digit line, and this load means is controlled by another voltage detection circuit whose detection voltage is higher than that of the voltage detection circuit 9 of FIG. 16. can do. In this case, when the level of the digit line drops to a value that no longer guarantees the operation of the readout circuit, the level of the digit line is increased by controlling the load means connected to the digit line, and the power supply voltage is increased to The operation of the X decoder 1 can be stopped when the value decreases to such a value that the operation of the X decoder 1 cannot be guaranteed.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the memory circuit of the embodiment, Figure 2 is a detailed circuit diagram of block _R11 in Figure 1, Figure 3 is a detailed circuit diagram of block RC1 in Figure 1, and Figure 4 is a detailed circuit diagram of block _R11 in Figure 1. is a timing chart of the memory circuit in Figure 1, Figure 5 is a detailed circuit diagram of blocks 7 and 8 in Figure 1, Figure 6 is a detailed circuit diagram of block 3 in Figure 1, and Figure 7 is a detailed circuit diagram of block 3 in Figure 1. A detailed circuit diagram of block BX or BY in Fig. 1, and Fig. 8 is a detailed circuit diagram of block BX or BY in Fig. 1.
Detailed circuit diagrams of 10 and 11, Figures 9 and 10
The figure is an operating waveform diagram of the memory circuit of Figure 1, Figure 11 is a characteristic curve diagram of the circuit of Figure 8, Figures 12 to 15 are circuit diagrams of other embodiments, and Figure 16 is the diagram of the circuit of Figure 1. FIG. 17 is a characteristic curve diagram of the circuit of FIG. 16. 1...X decoder, 2...Memory matrix, 3...Y decoder, 4...Column input/output circuit, 5...Write circuit, 6...Read circuit,
7...Write control circuit, 8...Read control circuit, 9...Power supply voltage detection circuit, 10...Pulse generation circuit, 11...Switch circuit.

Claims (1)

[Scope of Claims] 1. A memory cell, a pair of digit lines to which the memory cell is connected, a pair of common data lines, and a circuit that is controlled by a selection signal to connect the pair of digit lines and the pair of common data lines. a second switch means coupled to the pair of common data lines and controlled by a timing signal to reduce a potential difference between the pair of common data lines; and a second switch means responsive to a control signal. a control circuit for forming the timing signal for operating the second switch means for a predetermined period after the control signal is changed. 2 The above memory cell consists of a MISFET that constitutes a flip-flop and a transmission gate MISFET,
2. A memory circuit according to claim 1, wherein said first and second switch means are comprised of MISFETs. 3. The memory circuit according to claim 1 or 2, wherein the control circuit is configured to form the timing signal based on a chip selection signal and a write control signal.