JPH0263149A - Package for semiconductor integrated circuit use - Google Patents

Abstract

PURPOSE:To simplify a printed wiring pattern by a method wherein one part of the rear surface of at least one of first-kind electric terminals of electric terminals in one row out of electric terminals arranged in two rows is set on a level which is nearly identical to that of the top surface of a second-kind electric terminal in the other row. CONSTITUTION:This package is constituted of a package main body 10 and electric terminal rows 20a, 20b stretched to both sides of the main body. One electric terminal row 20a of this package is shaped so as to be identical to electric terminals used in a conventional flat package. At electric terminals 21a, 21b, 21c in one part of the other electric terminal row 20b, a level of the top surface of the electric terminals in one row is situated at a level of their rear surface; their width is made narrower than that of the electric terminals in the one row. As a result, when such packages are arranged in parallel and placed on a orinted-circuit board, individual electric terminals can be piled up and connected electrically.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor integrated circuit, and more particularly, it has electrical terminals arranged in two parallel rows, and the electrical terminals are arranged horizontally. This relates to a growing type of package (hereinafter referred to as a flat package).

[Prior art]

A flat package is known as one type of package that houses a semiconductor integrated circuit chip. Figure 5 shows the appearance of such a flat package. As shown in this figure, the flat package main body 1 has two rows of electrical terminal rows 2a and 2b extending on both sides thereof.
Each of the electrical terminals a and 2b can be electrically connected to the wiring pattern on the lower printed wiring board. For example, a semiconductor memory chip is mounted within such a flat package. When multiple semiconductor memory devices of the same type are used, electrical terminals for data lines extending from each device are connected in parallel to a common data bus formed on a printed wiring board. . In order to mount a semiconductor memory element mounted in a flat package on a printed wiring board, its electrical terminals are brought into contact with electrical connections formed on the printed wiring board and fixed with solder or the like. The mounted state is shown in FIG. 6(a). The electrical connection portions 3.4 and the like formed on the printed wiring board 5 are electrically connected through desired wiring patterns 6.7, respectively.

[Problem to be solved by the invention]

However, in the conventional mounting method using a flat package as described above, a number of electrical connections corresponding to the number of electrical terminals of a semiconductor element are required, and furthermore, the number of electrical connections between these electrical connections is as desired. A wiring pattern was required for electrical connection. Therefore, as the number of semiconductor elements to be mounted increases, the wiring pattern becomes dramatically more complex, making design errors more likely to occur. Also, the distance between these adjacent electrical connections 3.4 is as shown in Fig. 6(b).
As shown in Figure 2, they must be insulated from each other, so a certain distance must be maintained.

Therefore, as the number of electrical connections increases, the area of the printed wiring board increases dramatically. Furthermore, as wiring patterns become more complex, the distance of signal wiring to semiconductor elements becomes longer, resulting in delays in electrical signals. Therefore, when a semiconductor memory element is mounted and used on such a printed wiring board, the speed of the entire system becomes slow, and the signal waveform deteriorates significantly, reducing the reliability of the entire system.

The present invention solves the above problems and provides a semiconductor integrated circuit package that can be mounted on a printed wiring board having a simplified wiring pattern, especially when the same type of elements are connected in series. The purpose is to provide.

[Means to solve the problem]

A package for a semiconductor integrated circuit according to the present invention is a package for a semiconductor integrated circuit having a package body and a plurality of electrical terminals arranged in two rows on both sides of the package body and extending in the horizontal direction, the package comprising: A part of the lower surface of at least one of the first type electric terminals in one row of the electric terminals arranged in the second row is substantially at the same level as the upper surface of the second type electric terminal in the other row. do.

[Effect]

Since the semiconductor integrated circuit package of the present invention is configured as described above, it is possible to directly connect a plurality of semiconductor elements without using wiring, and the semiconductor integrated circuit package mounted in such a package can be connected directly. The printed wiring pattern of the printed wiring board on which the element is mounted can be simplified.

〔Example〕

Embodiments according to the present invention will be described below with reference to the drawings.

Elements with the same reference numerals have the same functions, so duplicate explanations will be omitted.

FIG. 1 shows an external perspective view of a package for a semiconductor integrated circuit according to the present invention. As shown in this figure, a semiconductor integrated circuit package (hereinafter simply referred to as a package) includes a package body 10 and electrical terminal rows 20a and 20 extending on both sides of the package body 10.
It is composed of b. One row of electrical terminals 20a of this package has the same shape as the electrical terminals used in conventional flat packages, and some of the electrical terminals 21a and 21b of the other row of electrical terminals 20b.

21c has its lower surface at the level of the upper surface of the electrical terminals in one row, and its width is narrower than that of the electrical terminals in one row. Therefore, when such packages are placed in parallel on a printed wiring board, the electrical terminals overlap each other,
Can be electrically connected. Note that it is preferable that the electrical terminals in any of these rows can be electrically connected to the electrical connection portions on the printed wiring board, and also be electrically connected to the wiring patterns connected to the electrical connection portions.

FIG. 2 shows the connection structure of the package and the internal electrical connection structure.

FIG. 2(a) shows a side view of the semiconductor memory elements housed in the package in a connected state, and FIG. 2(b) shows a top view of the connected state of FIG. 2(a). , a partially exploded view showing the interior of the package.

As shown in these figures, electrical terminals 30a, 130b, 31a,
31b, 32a, and 32b are provided. The electrical terminal 30a of the package 30 is electrically connected to an electrical connection portion 41a formed on a printed wiring board 40, and the electrical connection portion 41a is electrically connected to a wiring pattern 50a.
are electrically connected with solder, etc. The electrical terminals 30b of the package 30 receive the electrical terminals 31a of the package 31 and are electrically connected to each other.
A is electrically connected to an electrical connection portion 41b of the printed wiring board 40, and this electrical connection portion 41b is electrically connected to the connected wiring pattern 50b by solder or the like.

Furthermore, the electrical terminal 31b of the package 31
The electrical terminals 32a of the printed wiring board 40 are electrically connected to each other.
1c, and is electrically connected by solder or the like to a wiring pattern 50c that is electrically connected to this electrical connection portion 41c.

Here, the electrical terminals 30a and 130b of the package 30 are electrically connected to each other as shown in FIG.
It is wire-bonded to the bonding pad 60a. Similarly, the electrical terminals 31a131b, 32a, and 32b of the package 31.32 are also connected to each other, and are wire-bonded to the bonding holes 61a, 62a, of the semiconductor chip 61, 62, respectively. By mounting the above package as shown in Figure 2, the number of electrical connections required in the past can be reduced to approximately 1/2, thereby simplifying the wiring pattern on the printed wiring board. can be converted into Therefore, more semiconductor elements can be mounted using a printed wiring board with the same area.

Specifically, static memory I of IK x 1 bit
A case will be described in which a memory circuit of IK bytes (1 byte - 8 bits) is constructed using eight C memory cells (hereinafter referred to as IK static memories). The wiring block diagram is shown in FIG. Such an IK bit static memory IC has an address input terminal A-A for 210-1024 bits, a data input terminal IN, a data output terminal OUT, and a write/read control terminal WE.

Selection control terminal C8 for IC selection, power supply and ground terminal V,
A total of 16 GND terminals are provided.

When such an IK bit static memory is housed in a conventional package to form an IK byte memory circuit, the number of electrical terminals provided on the memory element x the number of memory elements will be connected to the printed wiring board. will be needed above. Here, in the above memory circuit configuration,
Address terminals A-A9 can be connected in parallel with each other. Therefore, if these address terminals are accommodated in the package described above so as to serve as mutually connected terminals of the package, the number of electrical connections on the printed wiring board can be reduced.

Furthermore, when a three-stage shift register is constructed using three flip-flop ICs 70, 71, and 72 as shown in FIG. 4(a), the package is as shown in FIG. 4(b). By forming, arranging and connecting the terminals to each other, the number of electrical connections on the printed wiring board can be reduced.

The present invention is not limited to the above embodiments, and various modifications may be made.

Specifically, in the above embodiments, explanations are given regarding semiconductor memory devices and flip-flop devices, but the present invention is not limited to this, and can be applied to semiconductor devices in which multiple devices of the same type are connected in parallel or cascaded. be able to.

〔effect〕

In the package for a semiconductor integrated circuit of the present invention, by having the configuration as described above, a part of the interconnection between ICs can be performed without using the wiring pattern on the printed wiring board. Since the number of electrical connections on the top can be reduced and the wiring pattern can be simplified, it is possible to speed up signal transmission and reduce design errors in the wiring pattern.

In particular, mounting such a memory element in a package,
It is effective when configuring a system by connecting in parallel or when connecting in cascade using flip-flop ICs.

Terminal row, 30.31.32...semiconductor element, 4o...
- Printed wiring board, 41a, 41b, 41c... Electrical connection part, 50a150b15oc... Wiring pattern.

[Brief explanation of the drawing]

FIG. 1 is an external perspective view of a package for a semiconductor integrated circuit according to the present invention, FIG. 2 is a diagram showing an example in which the package shown in FIG. 1 is mounted on a printed wiring board, and FIG. 3 is a package of the present invention. Wiring diagram of a memory circuit to which this can be applied, Part 4
The figure shows the circuit configuration and mounting example of a three-stage shift register to which the package of the present invention can be applied, FIG. 5 is an external view of a conventional package, and FIG. It is a figure showing an example of implementation. 10...Package body, 20a, 20b...Electrical patent applicant Sumitomo Electric Industries Co., Ltd. Representative Patent Attorney Yoshi Hasekima
Fumiaki Terashima Practical example Figure 1 Implementation example Figure 2 Different application examples Figure 4

Claims (2)

[Claims] 1. A semiconductor integrated circuit package having a package body and a plurality of electrical terminals arranged in two rows on both sides of the package body and extending horizontally, the electrical terminals of one of the two rows of electrical terminals being arranged in two rows on both sides of the package body. A package for a semiconductor integrated circuit, wherein a portion of the lower surface of at least one type 1 electrical terminal of the terminals is approximately at the same level as the upper surface of the second type electrical terminal in the other row. 2. 2. The package for a semiconductor integrated circuit according to claim 1, wherein the width of the first type electric terminal is smaller than the width of the second type electric terminal in the other column.