JPH0263276B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static type semiconductor memory device composed of MISFETs (insulated gate field effect transistors).

An object of the present invention is to provide a semiconductor memory device with reduced power consumption.

According to this invention, as a constant current source
In order to reduce the power consumption of the sense amplifier that includes MISFET and amplifies the read signal from the memory cell and transmits it to the data output buffer circuit, the MISFET as the constant current source is activated by a predetermined control signal.
It is turned off when the chip is not selected or during a write operation.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 is a circuit diagram showing an embodiment of a static semiconductor memory device to which the present invention is applied.

Although not particularly limited, the semiconductor memory device shown in the figure is a well-known CMOS (complementary-metal-insulator-semiconductor)
It is formed on a single silicon single crystal semiconductor board using integrated circuit (IC) technology. Terminals V _DD , V _SS ,
AX ₁ , AX ₂ , D _OUT , D _io , , AY ₁ and
AY ₂ is its external terminal.

In FIG. 1, 1a to 1d are memory cells. These memory cells 1a to 1d
As shown with memory cell 1a as a representative,
High resistance load made of polycrystalline silicon layer
A flip-flop circuit composed of R ₁ and R ₂ and N-channel drive MISFETs Q ₁ and Q ₂ , and an N-channel type transmission provided between the input/output terminal of this flip-flop circuit and the input/output terminal of the memory cell. It consists of gates _MISFETQ3 and _Q4 .

These memory cells are arranged in a matrix. The gates of the transmission gates MISFETQ ₃ , Q ₄ , etc. of the memory cells arranged in the same row are commonly connected to the corresponding word line W ₁ or W ₂ , respectively. The input/output terminals of memory cells arranged in the same column are connected to a corresponding pair of bit (data) lines.
Connected to D ₁₀ , D ₁₁ or D ₂₀ , D ₂₁ .

In the above memory cell, the above resistor R ₁ is turned off to reduce power consumption _.
The MISFET Q ₂ has a current supply capability sufficient to prevent the information charge stored in the gate capacitance (not shown) from being discharged due to the drain leakage current. Similarly the resistance R ₂ is
When MISFETQ ₂ is off, it has enough current supply capability to prevent information charges at the gate of MISFETQ ₁ from being discharged by MISFETQ ₂ drain leakage current.

According to this embodiment, the semiconductor memory device
Despite being manufactured using CMOS technology, memory cells are of N-channel type as mentioned above.
It consists of a MISFET and a polysilicon resistance element.

When using the above memory cell, the chip area of the memory cell itself and the chip area of the memory cell array can be made smaller than when using other constituent memory cells.

For example, instead of the above resistors R ₁ and R ₂ , the above drive
In the case of a memory cell configured to use P-channel MISFETs that operate complementary to MISFETs _{Q 1} and Q ₂ , the P-channel MISFETs are larger chips than the polysilicon resistors R ₁ and R ₂ . The above P-channel MISFET and N-channel MISFET
Since MISFETs _{Q 1} and Q ₂ must be formed with a relatively large interval, the chip area of the memory cell itself and the memory cell array must be relatively large.

The complementary MIS memory cell described above consists of the P-channel MISFET and the N-channel MISFET in series.
It has the characteristic of exhibiting low power consumption characteristics by operating in a complementary manner with MISFET.

On the other hand, in _the memory cell shown in _FIG .
DC current is passed through MISFETQ ₁ and Q ₂ . However, the memory cell in FIG.
By setting the resistance values of R ₁ and R ₂ to high resistance values such as several megohms to several gigaohms,
It comes to exhibit sufficient low power consumption characteristics.

Although not shown, the N-channel type shown in Figure 1
The MISFET and P-channel MISFET are configured to have a polysilicon gate electrode.
Accordingly, the polysilicon resistance elements R ₁ and R ₂ are connected to the corresponding drive MISFET Q ₂
and the gate electrode of _Q1 .

With such a configuration, it is possible to further reduce the chip area of the memory cell.

In FIG. 1, the word line W ₁ is selected by the X address decoder circuit 2a, and the word line W ₂
is selected by the X address recorder circuit 2b. These X address recorder circuits 2a, 2b
have similar configurations, and although not particularly limited, as shown in detail with 2a as a representative, P-channel type MISFETQ ₁₈ as a load that is switch-controlled by a control signal.
and N-channel drive MISFETs Q ₁₆ and Q ₁₇ whose drains and sources are connected in parallel and whose respective gates are supplied with address signals bx ₁ and bx ₂ , and an N-channel output. It consists of an output buffer circuit composed of _MISFETQ19 , _Q20 and a complementary inverter circuit 1N.

Note that the illustrated X address recorder circuits 2a and 2b have an N-channel type drive in their NOR circuits.
P-channel MISFET that corresponds to MISFETQ ₁₆ and Q ₁₇ and operates complementary to each other.
Because the MISFET is not provided, it is constructed with relatively few circuit elements.

Also, MISFETQ ₁₉ in the output buffer circuit
is relatively large because the word line constitutes a relatively heavy capacitive load, but it is of an N-channel type rather than a P-channel type. Normally, when the same conductance characteristics are required, an N-channel MISFET can be made smaller than a P-channel MISFET, so the output buffer circuit described above can be made relatively smaller despite having an inverter circuit 1N. be able to. That is, the X address decoder circuits 2a and 2b can be made relatively compact.

Address signals supplied from a suitable device (not shown) are input to address buffer circuits BX ₁ and BX ₂ via address input terminals AX ₁ and AX ₂ . The above address buffer circuits BX ₁ and BX ₂ are
Non-inverted address signal depending on input address signal
Outputs bx ₁ , bx ₂ and inverted address signals ₁ and ₂ . The output address signals are appropriately selected and supplied to the X address recorder circuits 2a and 2b.

Each pair of bit lines D ₁₀ , D ₁₁ and D ₂₀ , D ₂₁ in the memory cell array is connected to a transmission gate MISFET _{Q 9} , Q ₁₀ and
Column switch circuit 4 composed of Q ₁₁ and Q ₁₂
It is connected to common bit lines CD ₀ and CD ₁ via.

The input terminals of the read output circuit 6 are connected to the common bit lines CD ₀ and CD ₁ , and the transmission game MISFETs _{Q 13} and Q ₁₄ are controlled by the write signal WE.
The output terminal of the write circuit 7 is connected through the. And between the common bit lines CD ₀ and CD ₁ is a P channel type for data reset.
MISFETQ ₁₅ is provided.

A pair of columns constituting the column switch circuit 4
Selection signals are supplied to the gates of MISFETs _{Q 9} , Q ₁₀ and Q ₁₁ , Q ₁₂ from Y address decoder circuits 3a, 3b, respectively. Y address decoder circuit 3
a is a P-channel type MISFETQ ₂₃ as a load resistance that is switch-controlled by a control signal'.
and an N-channel drive MISFETQ ₂₁ whose gates are supplied with address signals by ₁ and by ₂ , respectively.
It consists of Q ₂₂ .

Note that the Y address decoder circuits 3a and 3b are not provided with an output buffer circuit as in the X address decoder circuits 2a and 2b, since the corresponding load is light.

The readout circuit 6 is composed of a sense amplifier as described below and a data output buffer circuit that forms an output signal in three states (tri-state) including, but not limited to, an output floating state or a high output impedance state. It is.

The above data output buffer circuit uses the control signal CS
When is set to high level, the above common bit line
Outputs a signal at a level corresponding to the data signal supplied to CD ₀ and CD ₁ . Further, the data output buffer circuit causes its output terminal to be in the floating state when the control signal CS is set to a low level such as approximately ground potential.

8 is a control circuit which receives a write control signal via an external terminal and a chip selection signal via an external terminal, thereby controlling the read circuit 6 and the X address decoder circuits 2a, 2.
bY address decoder circuits 3a, 3b, data reset MISFETQ ₁₅ , transmission gate MISFETQ ₁₃ ,
Outputs control signals to control Q ₁₄ and bit line load MISFETs Q ₅ to Q ₈ .

When the chip selection signal is set to low level, the control signal CS is set to high level accordingly,
is set to low level. By the low level of the control signal', the X address decoder circuit 2a,
The bit line load MISFETs _Q5 to _Q8 are turned on.

The driving MISFET Q ₁ , Q ₂ in the memory cell coupled to the selected word line is connected to its transmission gate.
It is coupled to the corresponding pair of bit lines via MISFETQ ₃ and Q ₄ . As a result, the paired bit lines are given data corresponding to the data previously written in the memory cell. In this case, the above driving MISFETQ ₁ , Q ₂ ,
Load MISFET and transmission gate for the above bit line
Since a relatively large level of operating current is supplied via MISFETQ ₃ and Q ₄ , the above pair of bit lines receives a data signal that has a relatively large level and changes at a relatively high speed. will be supplied.

The data signals on the paired bit lines are supplied to the read circuit 6 via the column switch circuit 4 and the common bit lines CD ₀ and CD ₁ . the result,
Address signals supplied to address input terminals AX ₁ or AX ₂ and address input terminals AY ₁ or AY
Data in one memory cell selected by the address signal supplied to AY ₂ is read out via the readout circuit 6.

When the write control signal is set to low level,
In response to this, the control signal WE is set to high level,
Transmission gates MISFETQ ₁₃ and Q ₁₄ are turned on. The write data signal output from the write circuit 7 is supplied to the memory cell via the MISFETs _{Q 13} and Q ₁₄ and the column switch circuit 4. As a result, the data supplied to the external terminal _Dio will be written into the memory cell selected by the address signal.

Note that the power supply circuit 9 forms a voltage V _DD1 for compensating for variations in resistance values and for temperature compensation when the resistance elements R ₁ and R ₂ are used in memory cells. This power supply circuit 9 is not directly related to the present invention, so a description thereof will be omitted. As with other circuits, the power supply voltage V _DD1 of the memory cell may be a power supply voltage V _DD supplied from an external terminal V _DD .

In this embodiment, in order to reduce the power consumption of the sense amplifier constituting the readout circuit 6,
A sense amplifier SA as shown in FIG. 2 is used, and a control signal R generated by a control circuit 8 is used.
Its operation is controlled by .

That is, the readout circuit 6 uses the common bit line
It is composed of a sense amplifier SA that amplifies data signals from CD ₀ and CD ₁ , and a data output buffer circuit DOB that receives this amplified output signal. and,
The sense amplifier SA includes, but is not particularly limited to, N-channel type differential MISFETQ ₃₀ , Q ₃₁ , N-channel type MISFETQ ₃₃₂ as a constant current source provided on the common source side, and the above-mentioned differential MISFETQ _3J ,
It is composed of a P-channel type MISFET Q ₃₃ as a load provided at the drain of Q ₃₁ and a current mirror circuit formed by Q ₃₄ .

Data signals from the common bit lines CD ₁ and CD ₀ are supplied to the gates of the differential MISFETs Q ₃₀ and Q ₃₁ . Also, it can be used as a constant current source.
A control signal R is supplied to the gate of MISFETQ ₃₂ .

The above control signal R is a P-channel type MISFET Q ₃₅ , Q ₃₆ that receives a signal from an external terminal and a signal from the external terminal through an inverter circuit IV.
It is formed by a NOR circuit composed of N-channel type _MISFETQ37 and _Q38 .

As a result, when the external terminal signal is at a high level and a chip is not selected, the control signal R becomes a low level and the MISFETQ ₃₂ as a constant current source is turned off. Furthermore, even when a chip is selected where the external terminal signal is low level, in a write operation where the external terminal signal is low level, the control signal R becomes low level and the MISFET Q ₃₂ is turned off. In other words, as the constant current source,
The reason why MISFETQ ₃₂ operates at constant current is, in other words, the sense amplifier SA performs amplification operation because
Only in a read operation in which the external terminal is at a low level and the external terminal is at a high level, the control signal R becomes a high level, causing the sense amplifier SA to enter an amplifying operation state.

In this example, the sense amplifier
Since the SA is operated only during the readout period when its operation is necessary, compared to the conventional sense amplifier where the MISFETQ ₃₂ as a constant current source is always on (during chip non-selection and chip selection periods), Lower power consumption can be achieved.

Generally, in a semiconductor memory chip, the non-selection period occupies more than the selection period. Therefore, even if the current value of the constant current source is set to a relatively small value, if the constant current source is made to flow all the time like in a conventional sense amplifier, a large amount of power will be consumed.

On the other hand, in this embodiment, the constant current of the sense amplifier is made to flow only during the chip selection period and in the read operation, so that power consumption can be reduced.

The invention is not limited to the above embodiments.

The specific circuit configuration of the sense amplifier SA is the amplification
Any device may be used as long as it includes a MISFET and a constant current source that defines its operating current.

Also, it can be used as a constant current source for sense amplifier SA.
The MISFET is controlled by the chip select signal and
It may be turned off when the chip is not selected.

Further, the configuration of the static type semiconductor integrated circuit can take various embodiments.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the entire static type semiconductor integrated circuit showing one embodiment of the present invention, and FIG.
The figure is a circuit diagram showing an embodiment of the main part thereof. 1a to 1d...Memory cell, 2a, 2b...X address decoder circuit, 3a, 3b...Y address decoder circuit, 4...Column switch circuit, 5...Bit line load circuit, 6...Read circuit, 7...Write circuit, 8... Control circuit, 9...power supply circuit, 10...external power supply.

Claims (1)

[Claims] 1. A static type device that includes an amplified MISFET and a MISFET as a constant current source that defines its operating current, and is equipped with a sense amplifier that amplifies a read signal from a memory cell and transmits it to a data output buffer circuit. In this semiconductor memory device, the MISFET as the constant current source is controlled by a predetermined control signal.
A semiconductor memory device characterized in that the device is turned off during a write operation when a chip is not selected and when a chip is selected. 2. The semiconductor memory device according to claim 1, wherein the MISFET as a constant current source constituting the sense amplifier is provided on the common source side of the differential amplification MISFET. 3. The semiconductor memory device according to claim 1 or 2, wherein the semiconductor memory device is constituted by a complementary MIS circuit.