JPH0263298B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing semiconductor devices, particularly those in which a source or drain electrode is disposed in close proximity to a gate polycrystalline electrode such as a MOS/FET or MOS/SIT, or a semiconductor device such as a SIT or a semiconductor device. The present invention relates to an easy and precise manufacturing method for a semiconductor device such as a bipolar transistor in which a gate or base electrode is disposed in close proximity to a polycrystalline source (or drain) or emitter (or collector) electrode.

In recent years, as elements have become increasingly finer, precision in minute dimension processing and relative positioning in the mask transfer process has become a problem. For example, the position and width of the gate electrode relative to the source/drain electrode area of a MOS/FET must be highly accurate as the channel becomes shorter, and as the source or drain electrode area becomes smaller, the processing for contact holes must be made with finer dimensions.・Higher positioning accuracy will be required. Therefore, there is a limit to miniaturization depending on the performance of the mask transfer device, which in turn limits the performance and integration density of the IC. In order to overcome this, various self-
Alignment techniques have been developed. For example, there is a method of selectively forming the source and drain electrode regions using polycrystalline Si, which will serve as the gate electrode, as a mask, but this is effective when the conductivity type of the source and drain electrode regions is the same as that of the gate electrode. Therefore, there was a limit that it could not be used at different times. In addition, due to the relationship between contact dimensions and allowable positional errors, the dimensions of the source and drain regions are becoming increasingly tight. These problems are
The same applies not only to MOS/FETs but also to bipolar transistors and SITs. In particular, MOS・
The above-mentioned conventional self-alignment technology cannot be applied to a device such as SIT in which the conductivity types of the source/drain region and the polycrystalline gate electrode are preferably different from each other due to characteristics, and a new manufacturing method is currently desired.

The present invention has been made in view of the above-mentioned circumstances, and is particularly effective for semiconductor devices such as MOS/SIT in which polycrystalline gate electrodes of different conductivity types are provided close to source/drain regions of one conductivity type.・
The present invention provides a manufacturing method using alignment technology. In addition, the present invention is applicable to junction type SIT, bipolar
This provides a manufacturing process that can also be applied to transistors.

The manufacturing process of the present invention includes: (1) depositing a multilayer film of a nitride film (first thin film) and a second thin film (e.g. oxide film) from the bottom layer on the surface of one conductivity type region (for example, channel region) (2) A mask layer (e.g., resist layer) having openings in a predetermined first portion (e.g., corresponding to the source/drain region) is provided, and the second thin film is etched.(3) Using the mask layer, one conductive layer is etched through the first thin film. A first region with high impurity density (e.g., source/drain region) is provided in the mold region by ion implantation. (4) A third thin film (e.g., polycrystalline Si) is deposited, the mask layer is removed, and areas other than the first region are lifted.・Turn off and selectively leave the third thin film (5) The second thin film in the second part (e.g., corresponding to the gate oxide film region) and the third part in the first part (e.g., corresponding to the source/drain contact) ) above 3rd
Leave the thin film and use it as a mask to leave the first thin film, and then remove the second thin film to leave a multilayer film of the first and third thin films on the third part, and leave the first thin film on the second part ( 6) Perform selective oxidation. (7) After removing the first thin film on the second portion, perform a predetermined treatment (e.g., gate oxide film growth). (8) Perform selective oxidation on the second portion. mold
It consists of a series of steps: (9) selectively depositing a Si polycrystalline layer (Si polycrystalline layer) to form a second electrode; and (9) removing the first thin film in the first portion to provide a contact.

It has the feature that the high-density first region, the second electrode, and even the contact holes can be formed by performing the mask process at least three times. Also, the dimensions of the contact hole
Since the position can be determined in a self-aligned manner, this is advantageous for fine elements. Since the second portion serves as a substantial active region, very strict dimensional and positional accuracy is not required when forming the second electrode. Combined with these, there is an advantage that sufficiently fine elements can be manufactured using conventional transfer techniques, and high yields and low costs can be achieved.

The present invention will be explained in detail below using the drawings,
To reveal more.

FIGS. 1a to 1h are cross-sectional views showing steps in the manufacturing method of the present invention, taking MOS/FET as an example. In FIG. 1a, an oxide film 5, a nitride film (first thin film) 6, and an oxide film (second thin film) 7 are sequentially deposited on the surface of an n-type substrate (or well) 10 from below, and are formed to correspond to the source and drain. This is a cross section in which parts (first part) S and D are covered with a photoresist layer (mask layer) 8 having openings. The photoresist layer 8 is used as a mask for etching and ion implantation of the oxide film 7 in the next step, and for lift-off of the thin film. In this sense, for the resist layer 8, a PIQ-based organic material (including photosensitive materials), an electron beam resist, and an X-ray resist can also be used. In FIG. 1b, after selectively etching the oxide film 7 using the resist layer 8 as a mask, using the resist layer 8 as a mask, P-type impurity ions such as boron are applied to the first portions S and D. 6, implant P ⁺ drain, source region 1
1 and 12 are shown. Normally the oxide film 5 is
Since the thickness of the nitride film 6 is less than 500 Å, and the thickness of the nitride film 6 is less than 2000 Å, an energy of 100 KeV or more is sufficient for ion implantation. Thereafter, a Si thin film (third thin film) 9 is deposited over the entire surface by vapor deposition, sputtering, plasma CVD, ion beam deposition, or the like at a temperature below which the resist layer 8 does not deteriorate (FIG. 1c). The deposition of the Si thin film 9 is as follows:
It is desirable to have directionality so that it can be easily lifted off in the next process, and vapor deposition, ion beam, etc. are preferable. FIG. 1d shows a step of lifting off the Si thin film 9 by removing the resist layer 8 and leaving the Si thin film 19, 29 only on the first portions D, S, selectively forming the future gate area ( 2nd part) Step of leaving the oxide film 7 on G, etching the nitride film 6 using the Si thin films 19, 29 and the oxide film 7 on the second part as a mask, D,
The nitride films 16, 26, 36 on S (first part) and G (second part) are left, and the oxide film 7 on G is left.
This is a cross section after the process of removing. Oxide film 7 on G
In the mask process that leaves the Si thin films 19 and 29 on the first portions D and S as part of the mask, a positional accuracy of about 1/2 of the width of the D and S portions is sufficient, for example. ±0.5μm is sufficient. In addition, Si thin film 19,
If there are 29 unnecessary parts, they can be removed at the same time and can be made into a third part. In FIG. 1e, a selective oxide film 15 is shown using the nitride films 16, 26, and 36 as a mask.
A cross section of the field section is shown.

When the selective oxide film 15 in this step is thin as a field oxide film, a thick oxide film may be provided in advance. In this step, the Si thin films 19 and 29 are partially converted into co-partial oxide films 91 and 92.
In FIG. 1f, the nitride film 36 on the second portion G is removed using the oxide films 91 and 92 on the first portions D and S as a mask, and then the first portion D and S (or the third
oxide films 91, 92 (further Si thin film 1
9 and 29) to selectively form a gate oxide film 4 of a desired thickness. FIG. 1g shows a cross section of a polycrystalline layer deposited to form a gate electrode 3. FIG. The gate electrode 3 may be of either n-type or p-type, and in order to increase the threshold voltage, p-type can be used. After that, using the oxide film 25 on the gate electrode 3, the field oxide film 15, etc. as a mask,
The nitride films 16 and 26 on the part) and the oxide film 5 below are removed in a self-aligned manner, and a contact hole is formed.
CD and CS are provided, and drain/source electrodes 1 and 2 are formed to complete the process (Fig. 1h).

According to the above process, the dimensions and positions of the gate insulating film 4 and the drain/source contacts CD and CS are determined in a self-aligned manner, so that a highly precise microdevice can be realized. In addition, in this embodiment, the bottom layer oxide film 5
is inserted for strain relaxation, and is not essential to the present invention. In addition, as the second thin film 7
If a Si thin film is used, an oxide film can be selected as the third thin film 9, and other materials such as a high melting point metal and its silicide can also be used as one of the combinations.

Another embodiment of the present invention will be described using FIGS. 2a to 2f. This example is particularly advantageous for MOSSITs and short channel MOS/FETs. Second
FIG. 1A shows a cross section of the oxide film (second thin film) 7 side-etched using a mask layer 8 after undergoing the same process as that up to FIG. 1B. The side etching amount is the gate part (second part) to be formed in the future.
It is determined by the dimension of G, for example, 0.5 to 2.0μ. In addition, this side etching process is performed by ion implantation into the drain/source p ⁺ regions 11, 12.
The etching may be performed before or after the formation of the anisotropic etching, or by isotropic etching after anisotropic etching, or by isotropic etching alone, and both a wet process and a dry process can be used. FIG. 2b shows a cross section in which Si thin films 19 and 29 are left on the first portions D and S by the lift-off effect of the mask layer 8 after the Si thin film has been deposited. Since the mask layer 8 has an overhang,
Very easy to lift off. In FIG. 2c, the oxide film 7 in the field portion is removed by the mask process.
is removed, and the nitride film 6 is selectively etched using the oxide film 37 and the Si thin films 19, 29 (corresponding to the first or third part) remaining in the second part G as masks. FIG. 2d shows a cross section in which the oxide film 37 on the second portion G is removed by etching the entire surface, and the lowermost oxide film 5 is left on the first portions D, S and the second portion G. . The oxide film 5 may be side-etched if necessary, that is, if the dimensions are to be made finer.
In FIG. 2e, a selective oxide film 15 is provided, and in FIG.
CD, CS and electrodes 1 and 2 are installed, and the completed cross section is shown. In this way, by utilizing the side etching of the second thin film 7, the masking process described in FIG. 2c becomes simpler and a short gate length can be easily obtained. Also, like MOS/SIT, gate electrode 3 and drain/source p ⁺ regions 11, 12
Even if there is an offset between the substrate 10 and the substrate 10, there is no problem in operation; rather, shortening the gate length is preferable for improving the frequency.
The manufacturing method of the present invention is optimal for what is necessary to improve the off-state characteristics.

In the embodiment explained in FIGS. 1 and 2,
Other p ⁺ regions can be formed at the same time as the drain/source p ⁺ regions 11 and 12, and contact holes are also formed at the same time. Therefore, the third thin film (Si thin film) 9 can be removed for parts or parts that do not require contact, and a mask process can be used to remove the oxide film 7 on the field.

Using Figure 3 a to f, join type SIT or B
Another embodiment of the present invention will be described by taking SIT as an example. The first portion B in FIG. 3a corresponds to the p ⁺ gate region 14 and the n ⁺ substrate or buried layer 100.
is provided in the n ⁺ region 110 above. FIG. 3b shows a cross-section after depositing a third thin film (for example, a Si thin film) 9, and FIG. 3c shows a cross-section after side-etching a second thin film (for example, an oxide film) 7. This side etching can also be done by the process described in FIG. In this step, the shape and position of the source region (second portion) E are determined. In FIG. 3d, after the mask layer 8 is removed, the field part oxide film 7 and the Si thin film 9 in the first part (gate region) B which do not require contact are removed by a mask process, and then the nitride film 6 is selectively etched. The cross section is shown. As a result, the nitride film 64 and the Si thin film 49 remain on the contact part (third part) CB of the first part (p ⁺ gate region) 14, and only the nitride film 61 remains on the source part (second part) E. (The oxide film 71 will be removed by etching the entire surface in the next step). In FIG. 3e, a selective oxide film 15 is formed, and in FIG. 3f, the n ⁺ source region 111 is is formed via a polycrystalline electrode 101, and a gate contact is provided in a self-aligned manner to complete the electrode/wiring formation.

In this way, in this example, the treatment after opening the second portion E is different from the examples shown in FIGS. 1 and 2,
An n ⁺ source region 111, which is one of the main electrodes of the SIT, is provided. Further, as in this embodiment, there is an advantage that the contact hole can be formed in the third portion CB, which is a specific region of the first portion B, without changing the process. Although the explanation is for upright type SIT, it can also be applied to inverted type, and n ^- area 110
If a p region is provided in a part of the transistor, it can also be applied to an npn bipolar transistor. Furthermore, the second
A lateral pnp transistor can also be manufactured by applying the embodiment shown in FIG. 1 or 2 by changing the process after the partial opening. Furthermore, it is obvious that it can also be applied to JFET and horizontal JSIT.

Since the conductivity type of each region can be changed, the present invention is also applicable to integrated circuits including various types of transistors. Further, since it can be used not only for transistors but also for all devices having polycrystalline electrodes near high impurity density, its range of application is extremely wide. Furthermore, since microscopic devices can be created without using a special microfabrication transfer machine, this greatly contributes to the simplification and cost reduction of VLSI implementation.

[Brief explanation of drawings]

Figures 1a to 1h show the manufacturing method according to the present invention.
Cross-sectional diagram of the process order of the example applied to MOSFET, 2nd
Figures a to f are cross-sectional views of the process order of an example in which the manufacturing method of the present invention is applied to MOS/SIT, and Figures a to f are
FIG. 3 is a cross-sectional view along each step of an example in which the manufacturing method of the present invention is applied to a bonded SIT. 10,110...n-type region, 11...p ⁺ drain region, 12...p ⁺ source region, 4...gate oxide film, 3...gate electrode, 14...p ⁺ gate region, 100,111... ...n ⁺ area, 5, 15,
25... Oxide film, 6, 16, 26, 36, 61,
64...Nitride film (first thin film), 7, 37, 71...
...Oxide film (second thin film), 9, 19, 29, 49...
...Si thin film (third thin film), 8...mask layer, 20...
...Ion beam, S, D, B...first part, G,
E...Second part, CS, CD, CB...Third part.

Claims (1)

[Scope of Claims] 1. A step of depositing a multilayer film of a first thin film made of a nitride film and a second thin film different from the thin film from below on the surface of a semiconductor region of one conductivity type;
a step of selectively etching the second thin film by providing a mask layer having holes in some portions; and using the mask layer;
and providing a high impurity density first region by ion implantation into a portion corresponding to the first portion of the one conductivity type region through the first thin film, and after depositing a third thin film different from the second thin film, a step of leaving a third thin film on the first thin film of the first portion by a lift-off effect by removing the layer; and a second thin film of a predetermined second portion in the vicinity of the first portion; a step of leaving a third thin film in a third portion; and after leaving the first thin film using the remaining second and third thin films as masks, removing the second thin film and forming the first and second thin films in the third portion; ,
selectively leaving the first thin film on the second portion;
A step of forming a selective oxide film using the thin film as a mask, and a step of removing the first thin film in the second portion in a self-aligned manner, opening a part of the one conductivity type region, and performing a predetermined treatment are at least the same. a step of selectively depositing a semiconductor thin film covering the second portion to form a second electrode;
The portion of the first thin film is removed in a self-aligned manner to remove the first thin film.
A method for manufacturing a semiconductor device, comprising a step of forming a first electrode by opening a hole in a part of the region. 2. The semiconductor according to claim 1, wherein the selective etching of the second thin film using the mask layer includes over-etching by isotropic etching to provide an overhang in the mask layer. Method of manufacturing the device. 3. After providing the first region and before lifting off the third thin film by removing the mask layer, the second thin film is isotropically etched to narrow the width of the second portion. A method for manufacturing a semiconductor device according to item 1. 4. According to any one of claims 1 to 3, the second thin film is an oxide film, the third thin film is a semiconductor thin film, and the mask layer is a photosensitive or radiation-sensitive resist layer. A method for manufacturing a semiconductor device. 5. The first region is a source/drain region of opposite conductivity type provided across the one conductivity type region, and the second electrode is a one conductivity type polycrystalline layer and an oxide film is formed on the one conductivity type region. a gate electrode through which
Manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that a MOS transistor is formed by providing this oxide film by a predetermined treatment after opening the second partial hole. Method. 6. The first region is a gate region of an opposite conductivity type in which the one conductivity type region is a channel region, the second electrode is a semiconductor thin film of one conductivity type that is a source or a drain, and after the second partial opening 5. The method of manufacturing a semiconductor device according to claim 1, wherein the predetermined treatment is to form a junction type SIT by selectively adding impurities of one conductivity type or by not doing anything in particular. 7. A reverse conductivity type semiconductor in which the one conductivity type region is a base region formed in an opposite conductivity type region, the first region is a one conductivity type base electrode region, and the second electrode is an emitter or a collector. Claims 1 to 4 are characterized in that the transistor is a thin film, and the predetermined treatment after opening the second portion is to form a bipolar transistor by adding impurities of one conductivity type or by not doing anything in particular. A method for manufacturing a semiconductor device according to any one of the above.