JPH0263310B2 - - Google Patents
Info
- Publication number
- JPH0263310B2 JPH0263310B2 JP56192539A JP19253981A JPH0263310B2 JP H0263310 B2 JPH0263310 B2 JP H0263310B2 JP 56192539 A JP56192539 A JP 56192539A JP 19253981 A JP19253981 A JP 19253981A JP H0263310 B2 JPH0263310 B2 JP H0263310B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- concentration
- low concentration
- drain
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000006386 memory function Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Description
【発明の詳細な説明】
本発明の絶縁基板上の導伝型が異なる２種類の
半導体の組み合わせで、ゲート電極は見かけ上１
つであるにもかかわらず、制御信号の与え方によ
つて選択的に書き込み、読み出しが出来るメモリ
ー機能を有するMOSデバイスに関するものであ
る。制御信号により回路の状態をセツトする方式
は、フリツプフロツプ回路として従来から良く知
られている。通常のフリツプフロツプは５〜６ケ
のトランジスタあるいは抵抗等で構成されるが、
これらを集積して大規模メモリー等を構成しよう
とした場合、より素子数が少ないことが望まし
い。単なるメモリーとしては、トランジスタとキ
ヤパシタンスを各１ケ使用したセルが最も単純で
あるが、読み出しが破壊的であるという欠点があ
る。読み出しが非破壊で、かつ選択的に書き込み
と読み出しが可能なセルで、現在最も素子数が少
ないのは、トランジスタを３個使用したダイトミ
ツクタイプのフリツプフロツプである。DETAILED DESCRIPTION OF THE INVENTION In the combination of two types of semiconductors having different conductivity types on the insulating substrate of the present invention, the gate electrode is
However, it relates to a MOS device that has a memory function that allows selective writing and reading depending on how control signals are applied. A system in which the state of a circuit is set using a control signal is conventionally well known as a flip-flop circuit. A normal flip-flop consists of 5 to 6 transistors or resistors.
When attempting to integrate these to form a large-scale memory or the like, it is desirable that the number of elements be smaller. As a mere memory, a cell using one transistor and one capacitor is the simplest, but it has the disadvantage that reading is destructive. Among cells that can be read non-destructively and that can be selectively written and read, the cell that currently has the smallest number of elements is the diatomic flip-flop that uses three transistors.
そこで、さらに素子数の少ない回路について考
える。第１図に示す回路では、ｎチヤネルMOS
トランジスタの基板がＰチヤネルMOSトランジ
スタのソースに接続されており、ノード４を形成
している。又、両トランジスタのゲートが互いに
接続されて端子６を形成している。Ｐチヤネルト
ランジスタの基板５はフロート又は接地されてい
るとする。この回路で、先ず、端子１，２を接地
し端子６に負電圧を印加するとＰチヤネルトラン
ジスタがオン状態となり、端子３を接地するか負
電圧を印加するかによつてノード４の電位も接地
電位か、あるいはある定つた負電位になる。も
し、端子６が接地されているとＰチヤネルトラン
ジスタはオス状態なので、端子３の電位にかかわ
らずノード４は前の状態を保つことになる。次に
端子６に正電圧を印加すると、Ｐチヤネルトラン
ジスタはオフ状態でｎチヤネルトランジスタがオ
ン状態になる。このときｎチヤネルトランジスタ
のオン抵抗は端子６に一定の正電圧を与えても、
ノード４の電位によつて異なるので、先り述べた
方法でノード４の電位を決めておけば、ｎチヤネ
ルトランジスタのオン抵抗を記憶できることにな
る。この様な回路では、ノード４の電位は端子６
が負になつた時だけ端子３でコントロールできる
という選択性があり、また、ｎチヤネルトランジ
スタのオン抵抗は、端子１，２に電位差を与え、
さらに端子６が正に印加される時のみ、外部にオ
ン電流として選択的に、しかも非破壊的に読み出
すことができる。ここでｎチヤネルとＰチヤネル
トランジスタを逆転させ、各端子に与える電圧の
極性を逆にしても当然同様の動作をさせることが
できる。従つて、本発明の目的は前記等価回路を
見かけ上１つのゲートで実現し、より小さな占有
面積でありながら制御信号によつて選択的に情報
を書き込み、しかも非破壊で読み出す様なメモリ
ー機能を有するMOSデバイスを提供することに
ある。 Therefore, we will consider a circuit with an even smaller number of elements. In the circuit shown in Figure 1, an n-channel MOS
The substrate of the transistor is connected to the source of the P-channel MOS transistor, forming node 4. Further, the gates of both transistors are connected to each other to form a terminal 6. It is assumed that the substrate 5 of the P-channel transistor is floating or grounded. In this circuit, first, when terminals 1 and 2 are grounded and a negative voltage is applied to terminal 6, the P channel transistor is turned on, and depending on whether terminal 3 is grounded or a negative voltage is applied, the potential of node 4 is also grounded. potential, or a certain negative potential. If the terminal 6 is grounded, the P channel transistor is in the male state, so the node 4 will maintain its previous state regardless of the potential of the terminal 3. Next, when a positive voltage is applied to the terminal 6, the P channel transistor is turned off and the n channel transistor is turned on. At this time, even if a constant positive voltage is applied to terminal 6, the on-resistance of the n-channel transistor is
Since it differs depending on the potential of node 4, if the potential of node 4 is determined by the method described above, the on-resistance of the n-channel transistor can be memorized. In such a circuit, the potential of node 4 is equal to the potential of terminal 6.
There is selectivity in that it can be controlled by terminal 3 only when
Furthermore, only when a positive voltage is applied to the terminal 6, it is possible to selectively and non-destructively read out the on-current to the outside. Naturally, the same operation can be achieved even if the n-channel and p-channel transistors are reversed and the polarity of the voltage applied to each terminal is reversed. Therefore, an object of the present invention is to realize the above-mentioned equivalent circuit with a single gate, and to provide a memory function that allows information to be written selectively in response to a control signal and read out non-destructively, while occupying a smaller area. Our goal is to provide MOS devices with
本発明のMOSデバイスは、絶縁基板上に形成
した島状半導体層の相離した少くとも２つの部位
に高濃度第１導伝型部を設けてソース・ドレイン
となし、これら少なくとも２つの部位に高濃度第
１導伝型部を設けてソース・ドレインとなし、こ
れら少くとも２つの高濃度第１導電型部にはさま
れた部位およびこの部位から延在する少くとも一
部の部位を中濃度第２導伝型となし、この中濃度
第２導伝型部の延在部に続けて第１導伝型もしく
は第２導伝型の低濃度部を設け、この低濃度部に
続けてこの低濃度部をはさむように前記中濃度第
２導伝型部と向い合うように高濃度第２導伝型部
を設けてソース・ドレインとなし、前記中濃度第
２導電型部上及び前記低濃度部上を覆う部位にゲ
ート絶縁膜を設け、さらにこのゲート絶縁膜上に
１つのゲート電極を設けて前記２つの高濃度第１
導伝型部にはさまれた部位の中濃度第２導伝型部
及び前記低濃度部を共通駆動する２つのチヤネル
となしたことを特徴としている。 In the MOS device of the present invention, high-concentration first conductivity type portions are provided in at least two separated portions of an island-shaped semiconductor layer formed on an insulating substrate to serve as a source and drain. A highly doped first conductivity type portion is provided to serve as a source/drain, and a portion sandwiched between at least two high concentration first conductivity type portions and at least a portion extending from this portion are centrally located. A low concentration part of the first conductivity type or the second conductivity type is provided following the extended part of the medium concentration second conductivity type part, and following this low concentration part, A high concentration second conductivity type portion is provided to sandwich this low concentration portion and face the medium concentration second conductivity type portion to serve as a source/drain, and a high concentration second conductivity type portion is provided above the medium concentration second conductivity type portion and A gate insulating film is provided in a region covering the low concentration part, and one gate electrode is further provided on this gate insulating film to cover the two high concentration first parts.
The present invention is characterized in that the medium concentration second conductivity type portion sandwiched between the conduction type portions and the low concentration portion are formed as two channels that commonly drive.
以下に本発明の典型的な一実施例につき、その
構造と動作原理について説明する。この実施例で
は第１導伝型半導体にｎ型第２導伝型半導体にＰ
型を仮定するか、逆の場合も印加電圧の極性がか
わるだけで動作は全く同じであり、これも当然本
発明に含まれる。 The structure and operating principle of a typical embodiment of the present invention will be explained below. In this embodiment, the first conductivity type semiconductor is n-type, the second conductivity type semiconductor is P
Even if the type is assumed or vice versa, the operation is exactly the same just by changing the polarity of the applied voltage, and this is naturally included in the present invention.
第２図に本発明のMOSデバイス平面図を製造
工程順に追つて示す。 FIG. 2 shows plan views of the MOS device of the present invention in the order of manufacturing steps.
第２図ａは、絶縁基板上のＴ字型真性島状シリ
コン全体に1011ケ／cm2程度のボロンをイオン注入
した後、レジストをマスクとして1013ケ／cm2程度
のボロンをイオン注入して低濃度のボロンドープ
領域１５と普通濃度のボロンドープ領域１４を形
成したところである。第２図ｂは薄いゲート酸化
膜を島状シリコンの全面に成長させ、CVDポリ
シリコンを約4000Åたい積した後、リンを
1018ケ／cm2程度イオン注入し、しかる後にエツチ
ングでゲート電極１６を形成した所である。 Figure 2a shows boron ions of about 10 11 ions/cm 2 implanted into the entire T-shaped intrinsic silicon island on an insulating substrate, and then boron ions of about 10 13 ions/cm 2 implanted using a resist as a mask. A low concentration boron doped region 15 and a normal concentration boron doped region 14 are now formed. In Figure 2b, a thin gate oxide film is grown on the entire surface of the silicon island, and after CVD polysilicon is deposited to a thickness of approximately 4000 Å, phosphorus is removed.
This is where the gate electrode 16 was formed by implanting ions at a rate of about 10 18 ions/cm 2 and then etching.
第２図ｃはCVD酸化膜等をマスクとしてリン
を５×1015／cm2程度注入して、ソース・ドレイン
領域１１，１２を形成し、さらにCVD酸化膜等
を利用してボロンを５×1015／cm2程度注入してコ
ントロール端子１３を形成した所である。このあ
と、ソース１１、ドレイン１２、コントロール端
子１３及びゲート１６に各々メタル配線１７を施
したものが、本発明のMOSデバイスとなる。こ
の様にして完成した所を、一部切り欠いた断面図
として第３図に示す。この様な構造のMOSデバ
イスに於いては高濃度のｎ型領域１１，１２をソ
ース・ドレインとし、普通濃度のＰ型領域１４を
基板とし、高濃度ｎ型ポリシリコン１６をゲート
としたｎチヤネルMOSトランジスタが形成され
ており、高濃度のＰ型領域１３と普通濃度のＰ型
領域１４をソース・ドレインとし、低濃度のＰ型
領域１５を基板とし、高濃度ｎ型ポリシリコン１
６をゲートとしたＰチヤネルMOSトランジスタ
が形成されているとみなせる。ＰチヤネルMOS
トランジスタはゲートがｎ型でしかも、絶縁基板
上に形成されているので、閾値はφV以下のエン
ハンス型の動作をする。従つてこのデバイスは第
１図の回路を見かけ上１つのゲートで、しかもコ
ンパクトに実現していることになり、先に述べた
動作方法により選択的に情報を書き込み、しかも
非破壊で読み出すことができる。 In Figure 2c, phosphorus is implanted at approximately 5×10 15 /cm 2 using a CVD oxide film as a mask to form source/drain regions 11 and 12, and then boron is implanted at 5× using the CVD oxide film or the like. This is where the control terminal 13 was formed by implanting about 10 15 /cm 2 . Thereafter, a metal wiring 17 is provided to each of the source 11, drain 12, control terminal 13, and gate 16, resulting in the MOS device of the present invention. The part completed in this manner is shown in FIG. 3 as a partially cutaway sectional view. In a MOS device having such a structure, an n-channel is formed in which the highly doped n-type regions 11 and 12 are used as sources and drains, the normally doped p-type region 14 is used as a substrate, and the highly doped n-type polysilicon 16 is used as a gate. A MOS transistor is formed, in which a heavily doped P-type region 13 and a normally doped P-type region 14 are used as a source and drain, a lightly doped P-type region 15 is used as a substrate, and a highly doped n-type polysilicon layer 1 is formed.
It can be considered that a P-channel MOS transistor with 6 as the gate is formed. P channel MOS
Since the transistor has an n-type gate and is formed on an insulating substrate, the transistor operates as an enhanced type with a threshold value of φV or less. Therefore, this device apparently realizes the circuit shown in Figure 1 with one gate and is compact, and can selectively write information and read it non-destructively using the operation method described above. can.
以上の説明では、説明の便宜上典型的で、しか
も簡単な一実施例についてのみ述べて来たが、本
発明は、この様な実施例のみに限定されるもので
はない。たとえば、第２図ｃの低濃度のＰ型領域
は請求の範囲で示した様に低濃度のｎ型あるいは
π型でも良い。 In the above description, only one typical and simple embodiment has been described for convenience of explanation, but the present invention is not limited to only such an embodiment. For example, the low concentration P type region in FIG. 2c may be a low concentration n type or π type as shown in the claims.
第１図は本発明のデバイスの等価回路を示して
おり、第２図ａ，ｂ，ｃは本発明のデバイス構造
を製造工程を追つて説明したものであり、第３図
は典型的な一実施例につき３次元的にその構造を
示したものである。図中の記号は、それぞれ次の
ものに対応する。
１……ｎチヤネルMOSトランジスタのドレイ
ン、２……ｎチヤネルMOSトランジスタのソー
ス、３……ＰチヤネルMOSトランジスタのドレ
イン、４……ｎチヤネルMOSトランジスタの基
板とＰチヤネルMOSトランジスタのソースの接
続節点、５……ＰチヤネルMOSトランジスタの
基板、６……ｎチヤネルMOSトランジスタとＰ
チヤネルMOSトランジスタの各ゲートの接続節
点、１１……高濃度ｎ型領域、１２……高濃度ｎ
型領域、１３……高濃度Ｐ型領域、１４……普通
濃度Ｐ型領域、１５……低濃度Ｐ型領域、１６…
…ゲートポリシリコン、１７……メタル配線、１
８……サフアイア基板、１９……ゲート酸化膜。
Figure 1 shows an equivalent circuit of the device of the present invention, Figures 2a, b, and c explain the device structure of the present invention step by step through the manufacturing process, and Figure 3 shows a typical one. The structure of an example is shown three-dimensionally. The symbols in the figure correspond to the following, respectively. 1... Drain of the n-channel MOS transistor, 2... Source of the n-channel MOS transistor, 3... Drain of the P-channel MOS transistor, 4... Connection node between the substrate of the n-channel MOS transistor and the source of the P-channel MOS transistor, 5...P channel MOS transistor substrate, 6...N channel MOS transistor and P channel
Connection node of each gate of channel MOS transistor, 11... Highly doped n-type region, 12... Highly doped n-type region
Type region, 13... High concentration P type region, 14... Normal concentration P type region, 15... Low concentration P type region, 16...
...Gate polysilicon, 17...Metal wiring, 1
8...Sapphire substrate, 19...Gate oxide film.
Claims (1)
た少くとも２つの部位に高濃度第１導伝型部を設
けてソース・ドレインとなし、これら少くとも２
つの高濃度第１導伝型部にはさまれた部位および
この部位から延在する少くとも一部の部位を中濃
度第２導伝型となし、この中濃度第２導伝型部の
延在部に続けて第１導伝型もしくは第２導伝型の
低濃度部を設け、この低濃度部に続けてこの低濃
度部をはさむように前記中濃度第２導伝型部と向
い合うように高濃度第２導伝型部を設けてソー
ス・ドレインとなし、前記中濃度第２導伝型部上
及び前記低濃度部上を覆う部位にゲート絶縁膜を
設け、さらに、このゲート絶縁膜上に１つのゲー
ト電極を設けて前記２つの高濃度第１導伝型部に
はさまれた部位の中濃度第２導伝型部及び前記低
濃度部を共通駆動する２つのチヤネルとなしたこ
とを特徴とするMOSデバイス。1 High concentration first conductivity type portions are provided in at least two separated parts of an island-shaped semiconductor layer formed on an insulating substrate to serve as a source and drain, and these at least two
A portion sandwiched between two high concentration first conductivity type portions and at least a portion extending from this portion are defined as a medium concentration second conductivity type portion, and an extension of this medium concentration second conductivity type portion A low concentration part of a first conductivity type or a second conductivity type is provided following the existing part, and facing the medium concentration second conductivity type part so as to sandwich this low concentration part following the low concentration part. A high concentration second conductivity type portion is provided to serve as a source/drain, a gate insulating film is provided at a portion covering the medium concentration second conductivity type portion and the low concentration portion, and further, the gate insulating film is One gate electrode is provided on the film to form two channels that commonly drive the medium concentration second conductivity type portion and the low concentration portion at a portion sandwiched between the two high concentration first conductivity type portions. A MOS device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56192539A JPS5893370A (en) | 1981-11-30 | 1981-11-30 | Mos device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56192539A JPS5893370A (en) | 1981-11-30 | 1981-11-30 | Mos device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5893370A JPS5893370A (en) | 1983-06-03 |
| JPH0263310B2 true JPH0263310B2 (en) | 1990-12-27 |
Family
ID=16292952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56192539A Granted JPS5893370A (en) | 1981-11-30 | 1981-11-30 | Mos device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893370A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9183980B2 (en) | 2010-09-29 | 2015-11-10 | Siemens Aktiengesellschaft | Arrangement and method for the compensation of a magnetic unidirectional flux in a transformer core |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0795394B2 (en) * | 1985-03-12 | 1995-10-11 | 日本電気株式会社 | Semiconductor memory cell |
| JPS6235559A (en) * | 1985-08-09 | 1987-02-16 | Agency Of Ind Science & Technol | Semiconductor memory |
| JP4457209B2 (en) * | 2002-04-10 | 2010-04-28 | セイコーインスツル株式会社 | Insulated gate thin film transistor and control method thereof |
| JP4880867B2 (en) * | 2002-04-10 | 2012-02-22 | セイコーインスツル株式会社 | THIN FILM MEMORY, ARRAY, ITS OPERATION METHOD AND MANUFACTURING METHOD |
-
1981
- 1981-11-30 JP JP56192539A patent/JPS5893370A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9183980B2 (en) | 2010-09-29 | 2015-11-10 | Siemens Aktiengesellschaft | Arrangement and method for the compensation of a magnetic unidirectional flux in a transformer core |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5893370A (en) | 1983-06-03 |
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