JPH0263397A - Video signal processor unit - Google Patents

Abstract

PURPOSE:To reduce the capacity of a time base correction memory and to lower the operating frequency by inputting a sampling frequency M to the time base correction memory while converting the frequency into a sampling frequency N with a relation of M:N in an integer ratio and M>N after an input video signal subjected to FM modulation is digitized and demodulated. CONSTITUTION:An input video signal 1 in the RF band before FM demodulations is A/D-converted by an A/D converter 2, demodulated by a digital FM demodulator 3, the sampling frequency is lowered by a sampling frequency converter 4 and the signal is fed to a time base correction memory 7. Thus, in comparison with the method where the input video signal at the RF band is A/D-converted, the signal with the sampling frequency without any modification is supplied to the time base correction memory, the quantity of data inputted to the time base correction memory 7 is reduced by the lowered sampling frequency to save the capacity of the memory 7. Moreover, the operating frequency for circuits after the sampling frequency converter 4 is lowered.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a video signal processing device that processes video signals reproduced in a VTR or video disc device, and particularly relates to a video signal processing device that processes video signals reproduced in a VTR or video disc device, and in particular, After A/D converting the video signal
The present invention relates to time axis correction means when performing M demodulation.

(Prior Art) In the playback system of a VTR or video disk device, the FM demodulator and de-emphasis circuit have conventionally been realized by analog circuits, but the playback FM video signal (RF multiplied signal is A/D converted, A method of realizing an FM demodulator and de-emphasis circuit by digital signal processing has been considered (for example, IECE 198B, Kobaya
shl:Experiments onVTRDlgl
[Al Signal Processing]
.

Further, the playback signal in a VTR or video disk device has time axis fluctuations. Conventionally, in order to remove time axis fluctuations, for example, as described in Japanese Patent Laid-Open No. 58-124385, a baseband video signal demodulated by an FM demodulator and a de-emphasis circuit of analog signal processing is After /D conversion, time axis correction is performed by inputting the data to a time axis correction memory.

When converting a video signal processing device into an IC, by combining the above two technologies, after directly A/D converting the RF video signal, FM demodulation, de-emphasis, and time axis correction can all be realized by digital signal processing. is possible.

In this case, the sampling frequency of the A/D converter is selected to be at least twice that of the FM-modulated RF band video signal, and compared to the case where time axis correction is performed after A/D converting the baseband video signal. It becomes more than double. For this reason, A/D
The amount of data output from the converter increases, and the capacity of the time axis correction memory increases significantly. Furthermore, as the sampling frequency increases, the operating frequency of the circuit increases accordingly, requiring a large amount of expensive circuit elements.

(Problem to be Solved by the Invention) If the FM demodulation and time axis correction are performed after directly digitizing the FM modulated video signal using an A/D converter, the capacity of the time axis correction memory increases. In addition, there is a problem in that the operating frequency of the circuit becomes high, which increases the cost.The present invention was made to solve these problems, and it is possible to avoid increasing the capacity of the time axis correction memory. Moreover, it is an object of the present invention to provide a video signal processing device that can perform FM demodulation and time axis correction by digital signal processing without increasing the operating frequency too much.

[Configuration of the Invention (Means for Solving the Problem) The present invention digitizes an FM-modulated input video signal using an A/D converter, demodulates it using a digital FM demodulator, and then samples it using a sampling frequency converter. The basic feature is that the frequency M is input into the time axis correction memory after being converted to a sampling frequency N that satisfies the condition that M>N is an integer ratio and M>N.

Here, the time axis fluctuation amount ΔT of the input FM video signal is ΔT≧
A time axis fluctuation component longer than 1/N, that is, the sampling period of the A/D converter, is corrected by controlling the write timing of the time axis correction memory. Also,
For time axis fluctuations, ΔT is 1/M〉8T1, that is, for time axis fluctuation components shorter than the sampling period of the sampling frequency converter, the sampling phase of the A/D converter must be controlled, or the sampling frequency converter and time axis Correction is performed by performing interpolation processing in the signal path between the correction memory and the correction memory. The time axis fluctuation components in the range of 1/N>ΔT≧1/M that cannot be corrected by these time axis corrections are corrected by controlling the thinning phase of the sampling frequency converter.

(Function) In this way, in the present invention, the input video signal in the RF band before FM demodulation is A/D converted, demodulated by the digital FM demodulator, and then the sampling frequency is lowered by the sampling frequency converter, and then the time axis correction is performed. Provides signals to memory. Therefore, compared to the method of A/D converting the input video signal in the RF band and then supplying the signal to the time axis correction memory at the same sampling frequency, the signal is input to the time axis correction memory by the lower sampling frequency. The amount of data stored is reduced, memory footprint is reduced, and the operating frequency after the sampling frequency converter is lowered.

(Example) The present invention will be explained in detail below.

FIG. 1 is a block diagram of a video signal processing device according to an embodiment of the present invention. In the figure, an input terminal 1 receives, for example, a reproduced RF signal from a VTR, that is, an FM-modulated video signal. This input video signal is converted into a digital signal by an A/D converter 2 and then demodulated by a digital FM demodulator 3. The output signal of the FM demodulator 3 is converted to a sampling frequency lower than the sampling frequency in the A/D converter 2 by a sampling frequency converter 4, and then guided to a de-emphasis circuit 5.
This becomes a baseband video signal with time axis fluctuations. This baseband video signal is delayed by a video delay device 6 for a certain period of time, and written into the time axis correction memory 7 under the control of the write control circuit 26. The contents of the time axis correction memory 7 are read out under the control of the readout control circuit 27, converted into an analog signal by the D/A converter 8, and further led to the output terminal 1o via the low-pass filter 9.

The reference clock generator 11 generates a reference clock signal 12 having a frequency that is more than twice the highest frequency of the input video signal arriving at the input terminal 1. The A/D converter 2 uses the clock changeover switch 14 to output the reference clock signal 12 during the horizontal blanking period of the input video signal, and the signal obtained by phase modulating the reference clock signal 12 by the clock phase modulator 13 during the video period. Each is supplied as a sampling clock signal. The same clock signal as this sampling clock signal is also supplied to the FM demodulator 3 and the sampling frequency converter 4. In the sampling frequency converter 4, a clock signal 17 obtained by dividing the basic clock signal 12 by a frequency divider 16 is sent to a thinning phase control circuit 18.
Supplied via. The clock signal 19 output from the thinning phase m control circuit 18 is sent to the de-emphasis circuit 5.
and is also supplied to the video delay device 6. The clock signal 17 is also supplied to the read control circuit 27 .

The output signal of the de-emphasis circuit 5 is input to a sync separator 20, where the horizontal sync signal is separated.

The separated horizontal synchronization signal is input to the burst flag generator 21, and a burst flag is generated based on the burst signal for detecting time axis fluctuations inserted into the blanking section of video No. 12. The burst flag is input to the time axis variation detector 22.

The baseband video signal output from the de-emphasis circuit 5 and the clock signal 17 from the frequency divider 16 are also input to the time axis variation detector 22 .

- The time axis fluctuation detector 22 samples the burst signal in the baseband video signal at the timing of the clock signal 17 using the burst flag as a reference, detects the phase difference between the burst signal and the clock signal 17, and calculates the phase difference between the burst signal and the clock signal 17. The phase difference is converted into a time axis fluctuation amount ΔT of the input video signal. Then, this time axis fluctuation amount ΔT is calculated by dividing the period of the clock signal 17 (the reciprocal number 17N of the sampling frequency in the sampling frequency converter 4) or more, and the period of the reference clock signal 12 (the reciprocal number of the sampling frequency in the A/D converter 2). 1/M) and the period of the clock signal 17 is 1/M).
ΔT≧1/N, 1/M>ΔT.

First to third detection outputs 2B and 24.25 are generated corresponding to each component of 1/N>ΔT≧1/M, respectively. 1st
The detection output 23 is supplied to a write control circuit 27, which controls the write address generation timing of the time axis correction memory 7. That is, the write control circuit 26 basically resets the write address of the time axis correction memory 7 based on the timing of the synchronization signal separated by the synchronization separation circuit 20, but when the first detection output 23 is given, this detection The reset timing is controlled according to the value of the output 23, and a write address is generated.

The second detection output 24 is supplied to the clock phase modulator 13 and modulates the phase of the sampling clock signal applied to the A/D converter 2, that is, the sampling phase of the A/D converter 2.

Furthermore, the third detection output 25 is output from the thinning phase control circuit 18.
is supplied to control the thinning phase in the sampling frequency converter 4. Here, the thinning phase refers to the phase of the sampling points thinned out in the sampling frequency converter 4.

Next, the operation shown in FIG. 1 will be explained with reference to the time chart shown in FIG. Note that FIG. 2 shows the sampling frequency M in the A/D converter 2 and the sampling frequency converter 4.
The ratio of the sampling frequency N of the output signal at is M:
This is an example of the case of N-2:1, where (a) is the waveform of the burst signal supplied to the time axis variation detector 22, (b) is the sampling point by the clock signal 17 in the time axis variation detector 22, (C) is the sampling point in A/D converter 2 by the sampling clock signal after being modulated by clock phase modulator 13, (d) is (e) thinned out to 1/2 in sampling frequency converter 4. The later sampling points are shown respectively.

The clock changeover switch 14 selects the reference clock signal 12 during the horizontal blanking period which is the operating period of the time axis variation detector 22, and the thinning phase control circuit 18 also outputs the clock signal 17 as the clock signal 19.

Now, it is assumed that the sampling phase of the burst signal in the time axis variation detector 22 is as shown in FIG. 2(b). Since the time axis fluctuation amount ΔT of the input video signal at this time is the sum of the component of ΔTl-1/M and the component of ΔT2 less than 611, the amount of time axis variation ΔT of the input video signal ≧1/N
The first detection output 23 corresponding to is 0, and 1/M>ΔT
The second detection output 24 corresponding to ΔT2 has a value corresponding to ΔT2, and the third detection output 25 corresponding to 1/N>ΔT≧1/M has a value corresponding to ΔTl. In this case, the clock phase modulator 13
The phase of the clock signal 12 is controlled by ΔT2, and the clock signal 15 after this phase control is supplied as a sampling clock signal to the A/D converter 2 in the next video signal period by the changeover switch 14. ,A/
The sampling phase in the D converter 2 is as shown in FIG. 2(e).

Next, the output data of the A/D converter 2 is inputted to the sampling frequency converter 4 via the digital FM demodulator 3, where the sampling frequency is lowered by half from M to N, and the baseband video signal is Frequency components outside the band are sufficiently suppressed.

The sampling frequency converter 4 reduces the sampling frequency to 1/2 by thinning out every other sampling point in FIG. 2(C) in the A/D converter 2. is controlled by the decimation' phase control circuit 18 in accordance with the value of the third detection output 25 (corresponding to ΔT1) of the time axis fluctuation detector 22. As a result, the phases of the sample points of the burst signal are 0', 90°, 180°,
It becomes 270°. The output signal of the sampling frequency converter 4 is written to the time axis correction memory 7 via the de-emphasis circuit 5 and the video delay device 6 at a timing controlled by the write control circuit 26, and then written to the read control circuit 27.
The D/A
By converting the signal back into an analog signal via the converter 8 and the low-pass filter 9, a time-base corrected video signal is obtained from the output terminal 10.

Figure 3 shows the sampling frequency M in the A/D converter 2.
This is an example in which the ratio of the sampling frequency N of the output signal of the sampling frequency conversion circuit 4 is M:N=7:3, and (a) shows the waveform of the burst signal supplied to the time axis fluctuation detector 22; (b) shows the sampling point of the clock signal 17 in the time axis variation detector 22, and (C) shows the sampling point of the A/D converter 2 when the reference clock signal 12 is used as the sampling clock signal. The time axis variation detector 22 detects the amount of time axis variation ΔT, which is 1
/N>ΔT≧17M1, that is, the component ΔT1 that is greater than or equal to the sampling period of the A/D converter 2 and less than the output period of the sampling frequency converter 4, and 1/M>ΔT1, that is, the A/D
It is decomposed into a component ΔT2 which is less than the sampling period of converter 2. Then, based on the time axis fluctuation component of ΔT2, A
By phase modulating the sampling clock signal supplied to the A/D converter 2, the sampling points at the A/D converter 2 become as shown in FIG. 3(d). Next, in the sampling frequency converter 4, each sample in (d) is interpolated at a frequency that is the least common multiple of M and N, and the phase shown in FIG. A sampling point is selected. As a result, the phase of the sample point of the burst signal in the output signal of the sampling frequency converter 4 is 0090°, 18° as shown in FIG. 3(C).
The angles become 0° and 270°, and time axis correction is performed.

・FIG. 4 shows another embodiment of the present invention, in which the clock phase modulator 13 and clock changeover switch 14 in FIG.
, so that the clock signal 12 is always supplied to the A/D converter 2, and the de-emphasis circuit 5
An interpolation circuit 28 is inserted between the video delay device 6 and the video delay device 6.

The interpolation circuit 28 corresponds to a component of 1/M>ΔT of the time axis fluctuation amount ΔT detected by the time axis fluctuation detector 22, that is, a time axis fluctuation component ΔT2 that is less than the sampling period of the A/D converter 2. Then, the sample values of the sampling points of phase 0', 90°, 180', and 270°, which are indicated by the symbol x in FIG. 2(a), are interpolated using the sample values of the sampling points before and after that. As a result, the time axis fluctuation component of ΔT2 is corrected in the same way as the clock phase modulation by the clock phase change unit A 2 shown in FIG.

[Effects of the Invention] According to the present invention, the input video signal which is FMl&modulated is A/
After being digitized by a D converter and demodulated by a digital FM demodulator, the sampling frequency M is converted to a sampling frequency N where M>N is an integer ratio and satisfies the MAH condition, and then stored in the time axis correction memory. Compared to the method of A/D converting the input video signal in the RF band and inputting the signal directly to the time axis 1+1 positive memory, by inputting it, it is possible to reduce the time axis performance and the capacity of the E memory. Since the operating frequency after the sampling frequency converter can be lowered, it is possible to significantly reduce costs.

In addition, when a sampling frequency converter is provided in this way, correction using a conventional time axis correction memory or sampling phase control in an A/D converter requires 1/N〉8T.
Although it is not possible to correct the time axis fluctuation component of the time axis fluctuation amount in the range of ≧1/M, the present invention can easily correct such time axis fluctuation components by controlling the thinning phase of the sampling frequency converter. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, in which the ratio of the sampling frequency of the A/D converter to the sampling frequency of the output signal of the sampling frequency converter is 2:1. Figure 3 is a time chart showing the operation when the sampling frequency ratio is 7=3.
FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. 2... A/D converter, 3... Digital FM demodulator, 4... Sampling frequency converter, 7... Time axis correction memory, 13... Clock phase modulator,] 8...
- Thinning phase control circuit, 22... time axis fluctuation detector,
28...Interpolation circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) An A/D converter that converts an FM-modulated input video signal into a digital signal, and a digital F converter that receives the output signal of this A/D converter as input.
M demodulator; a sampling frequency converter that converts the sampling frequency M of the output signal of this digital FM demodulator to a sampling frequency N that satisfies the condition that M:N is an integer ratio and M>N; and this sampling frequency A time axis correction memory provided at a stage subsequent to the converter detects the amount of time axis fluctuation of the input FM video signal, and detects the amount of time axis fluctuation of the input FM video signal, and for the time axis fluctuation component where the amount of time axis fluctuation ΔT is ΔT≧1/N, the time axis The correction is made by controlling the write timing of the correction memory, and the time axis fluctuation component of 1/M>ΔT is corrected by controlling the sampling phase of the A/D converter, and 1/N>ΔT≧1/ A video signal processing device comprising: means for correcting the time axis fluctuation component of M by controlling a thinning phase of the sampling frequency converter. (2) An A/D converter that converts an FM-modulated input video signal into a digital signal, and a digital F converter that receives the output signal of this A/D converter as input.
M demodulator; a sampling frequency converter that converts the sampling frequency M of the output signal of this digital FM demodulator to a sampling frequency N that satisfies the condition that M:N is an integer ratio and M>N; and this sampling frequency A time axis correction memory provided at a stage subsequent to the converter detects the amount of time axis fluctuation of the input FM video signal, and detects the amount of time axis fluctuation of the input FM video signal, and for the time axis fluctuation component where the amount of time axis fluctuation ΔT is ΔT≧1/N, the time axis The correction is made by controlling the writing timing of the correction memory, and for the time axis fluctuation component of 1/M>ΔT, by performing interpolation processing in the signal path between the sampling frequency converter and the time axis correction memory. and a means for correcting a time axis fluctuation component of 1/N>ΔT≧1/M by controlling a thinning phase of the sampling frequency converter.