JPH026346U - - Google Patents
Info
- Publication number
- JPH026346U JPH026346U JP8206588U JP8206588U JPH026346U JP H026346 U JPH026346 U JP H026346U JP 8206588 U JP8206588 U JP 8206588U JP 8206588 U JP8206588 U JP 8206588U JP H026346 U JPH026346 U JP H026346U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- input logic
- combination
- data bus
- soset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 4
- 230000005856 abnormality Effects 0.000 claims description 3
- 238000012806 monitoring device Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案に係るＣＰＵ動作異常監視装置
の一実施例を示すブロツク構成図、第２図は従来
のＣＰＵ動作異常監視装置のブロツク図である。
１１……出力ポート群、１２……論理演算回路
、１３……監視用タイマ、１４……警報回路、１
５……ＣＰＵ、１６……データバス。
FIG. 1 is a block diagram showing an embodiment of a CPU operation abnormality monitoring apparatus according to the present invention, and FIG. 2 is a block diagram of a conventional CPU operation abnormality monitoring apparatus. 11...Output port group, 12...Logic operation circuit, 13...Monitoring timer, 14...Alarm circuit, 1
5...CPU, 16...Data bus.
Claims (1)
ムにおいて、ＣＰＵのデータバスから出力信号を
受けとるｎ個の出力ポートと、入力論理の組合わ
せから特定の組合わせを選択するｎ入力の論理演
算回路と、ソセツトがかかつてからあらかじめ設
定された時間が経過したことを判定する監視用タ
イマと、ＣＰＵの動作異常と判定されたときに表
示、転送等の処理を行う警報回路と、前記出力ポ
ート群に一定周期で特定の論理の組合わせを持つ
たパルス群を出力するソフトウエアとを持つこと
を特徴とするＣＰＵ動作異常監視装置。 In a system controlled by a microcomputer, there are n output ports that receive output signals from the data bus of the CPU, an n-input logic operation circuit that selects a specific combination from the combinations of input logic, and a soset. a monitoring timer that determines whether a preset time has elapsed since 1. A CPU operation abnormality monitoring device comprising software that outputs a group of pulses having a combination of logics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8206588U JPH026346U (en) | 1988-06-21 | 1988-06-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8206588U JPH026346U (en) | 1988-06-21 | 1988-06-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH026346U true JPH026346U (en) | 1990-01-17 |
Family
ID=31306832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8206588U Pending JPH026346U (en) | 1988-06-21 | 1988-06-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH026346U (en) |
-
1988
- 1988-06-21 JP JP8206588U patent/JPH026346U/ja active Pending