JPH0478741U - - Google Patents
Info
- Publication number
- JPH0478741U JPH0478741U JP12181890U JP12181890U JPH0478741U JP H0478741 U JPH0478741 U JP H0478741U JP 12181890 U JP12181890 U JP 12181890U JP 12181890 U JP12181890 U JP 12181890U JP H0478741 U JPH0478741 U JP H0478741U
- Authority
- JP
- Japan
- Prior art keywords
- control unit
- output
- timer
- key
- external devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Measurement Of Predetermined Time Intervals (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例を示す説明図、第２
図は出力モードの一例を示すタイミングチヤート
で、同図ａはレベルモードを示し、同図ｂはパル
スモードを示し、第３図は本考案の電源立上時に
おける作動を示す流れ図、第４図は本考案の主要
な作動を示す流れ図、第５図は本考案のシーケン
ス処理の作動を示す流れ図、第６図は本考案の自
動復帰処理の作動を示す流れ図である。
１……シーケンスタイマー、２……本体ボード
、３……パネル、４……制御部、９……第１出力
グループ、１０……第２出力グループ、１３，１
４……外部機器、１６……キー。
Fig. 1 is an explanatory diagram showing one embodiment of the present invention;
The figure is a timing chart showing an example of the output mode, where a shows the level mode, b shows the pulse mode, FIG. 3 is a flowchart showing the operation of the present invention at power-up, and FIG. 5 is a flowchart showing the operation of the sequence processing of the invention, and FIG. 6 is a flowchart showing the operation of the automatic return processing of the invention. 1...Sequence timer, 2...Main board, 3...Panel, 4...Control unit, 9...First output group, 10...Second output group, 13,1
4...external device, 16...key.
Claims (1)
出力信号に基づき共通のタイマ信号にしたがつて
シーケンス作動する複数の外部機器と、上記制御
部に所定の情報を入力するキーを備えたシーケン
スタイマーにおいて、上記キーを介して時間情報
のみを制御部へ入力可能にし、該制御部の出力側
に上記複数の外部機器からなる出力グループを複
数接続し、これらのグループを単独または並行し
てシーケンス作動可能にする一方、各外部機器の
出力を接点のＯＮ・ＯＦＦ作動モードとパルスモ
ードとに切り換え可能にし、かつ制御部を配設し
た本体ボードを、キーを配設したパネルに着脱可
能に装着したことを特徴とするシーケンスタイマ
ー。 A sequencer comprising: a control unit including a CPU and memory; a plurality of external devices that operate in sequence according to a common timer signal based on the output signal of the control unit; and a key for inputting predetermined information to the control unit. In the timer, only time information can be input to the control unit via the above keys, and multiple output groups consisting of the plurality of external devices described above are connected to the output side of the control unit, and these groups can be sequenced individually or in parallel. While enabling operation, the output of each external device can be switched between contact ON/OFF operation mode and pulse mode, and the main board with the control unit is removably attached to the panel where the key is installed. A sequence timer that is characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12181890U JPH088504Y2 (en) | 1990-11-22 | 1990-11-22 | Sequence timer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12181890U JPH088504Y2 (en) | 1990-11-22 | 1990-11-22 | Sequence timer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0478741U true JPH0478741U (en) | 1992-07-09 |
| JPH088504Y2 JPH088504Y2 (en) | 1996-03-06 |
Family
ID=31869649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12181890U Expired - Fee Related JPH088504Y2 (en) | 1990-11-22 | 1990-11-22 | Sequence timer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088504Y2 (en) |
-
1990
- 1990-11-22 JP JP12181890U patent/JPH088504Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH088504Y2 (en) | 1996-03-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |