JPH0263573U - - Google Patents
Info
- Publication number
- JPH0263573U JPH0263573U JP14334088U JP14334088U JPH0263573U JP H0263573 U JPH0263573 U JP H0263573U JP 14334088 U JP14334088 U JP 14334088U JP 14334088 U JP14334088 U JP 14334088U JP H0263573 U JPH0263573 U JP H0263573U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- electronic component
- shaped electronic
- insulating substrate
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims description 2
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案に係る突起を絶縁基板上に突設
した状態を示す平面図、第２図は本考案の要部を
示す部分拡大図、第３図は第２図Ｉ―Ｉ線断面図
、第４図は厚膜混成集積回路装置の１例を示す斜
視図である。
１０……絶縁基板、１１……配線パターン、１
２……突起、１３……チツプ状電子部品、１３ａ
……電極、１３ｂ……底面、１４……マウント個
所、１５……半田付け。
Fig. 1 is a plan view showing a state in which a protrusion according to the present invention is protruded on an insulating substrate, Fig. 2 is a partially enlarged view showing the main parts of the present invention, and Fig. 3 is a cross section taken along the line I--I in Fig. 2. 4 are perspective views showing an example of a thick film hybrid integrated circuit device. 10...Insulating substrate, 11...Wiring pattern, 1
2... Protrusion, 13... Chip-shaped electronic component, 13a
... Electrode, 13b ... Bottom surface, 14 ... Mounting point, 15 ... Soldering.
Claims (1)
にチツプ状電子部品の電極を直接半田付けするこ
とにより、上記チツプ状電子部品を絶縁基板上に
マウントしたものに於て、 上記絶縁基板のチツプ状電子部品マウント個所
に、チツプ状電子部品の底面と当接し、チツプ状
電子部品を若干傾斜させる突起を形成したことを
特徴とする混成集積回路装置。[Scope of Claim for Utility Model Registration] A chip-shaped electronic component mounted on an insulating substrate by directly soldering the electrodes of the chip-shaped electronic component to predetermined positions of a wiring pattern formed on the insulating substrate. . A hybrid integrated circuit device, characterized in that a protrusion is formed at the location where the chip-shaped electronic component is mounted on the insulating substrate, the protrusion coming into contact with the bottom surface of the chip-shaped electronic component and slightly tilting the chip-shaped electronic component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14334088U JPH0263573U (en) | 1988-10-31 | 1988-10-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14334088U JPH0263573U (en) | 1988-10-31 | 1988-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0263573U true JPH0263573U (en) | 1990-05-11 |
Family
ID=31410074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14334088U Pending JPH0263573U (en) | 1988-10-31 | 1988-10-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0263573U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025220064A1 (en) * | 2024-04-15 | 2025-10-23 | 株式会社Fuji | Circuit formation method and circuit formation device |
-
1988
- 1988-10-31 JP JP14334088U patent/JPH0263573U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025220064A1 (en) * | 2024-04-15 | 2025-10-23 | 株式会社Fuji | Circuit formation method and circuit formation device |