JPH0264751A - Data memory system - Google Patents

Abstract

PURPOSE:To improve using efficiency and to shorten data processing time by assigning data whose conditional changes are maximum 2<m> ways at every bit of (m) memories. CONSTITUTION:When data whose conditional changes are maximum 2<m> ways, are assigned and stored, for instance, to respective bits 1 to N of RAMs M1 and M2 having m=2, the data of the N>4 kinds of N>2<m> are written without vacant space, using efficiency is improved and data processing time can be shortened.

Description

[Detailed Description of the Invention] [Summary] Regarding a data storage method suitable for use when processing state transitions of a large amount of data by software using a CPU etc. 2m) The purpose is to make it possible to use a memory area in a state with good memory usage efficiency when storing data, and to also reduce data processing time.

When storing N (N>2m) types of data each having a maximum of 2m states of change, m memories are combined into a set, and each memory is configured to allocate and store the data for each bit. do.

[Industrial Application Field] The present invention relates to a data storage method suitable for use when processing state transitions of a large amount of data by software using a CPU or the like.

[Prior Art] FIG. 6 is a block diagram of a data processing device using a CPU. In FIG. 11 is a CPU, 12 is a ROM that stores a processing program, 13 is each of the above. R that remembers the data state
AM, 14 is an output port, and these input ports 10,
CPUII, ROM12. RAM13. Output port 14
are connected to each other via a pass line 15.

Here, as shown in FIG. 7, the RAM 13 has one storage area M1 to M for each data D1 to ON.
N [These storage areas M1 to MN are memory areas of, for example, 1 byte (8 bits) corresponding to addresses 1 to N], and the state of each data is stored in each storage area M1 to MN. For example, for data with four types of states, only two bits in the storage area are used, as shown in FIG. In addition, in Fig. 8, “0
For example, the state ``0'' is a state where no alarm has occurred,
A state of "01" ■ indicates, for example, a state in which an alarm has occurred for the first time, a state "10" indicates, for example, a state in which recovery has occurred after an alarm has occurred, and a state "■" of rllJ indicates, for example, a state in which an alarm continues to occur. .

By the way, data processing in such a data processing device is as shown in FIG. data D8
Processing such as comparison with the stored data corresponding to is performed and the new state (any state from ■ to ■) is saved (steps a2 and a3).

After that, in step a4, check the processing results, and if the results indicate that there is a problem, output a signal from the output port 14, turn on a lamp, etc. (step a5), and notify the occurrence of an alarm. .

9. If there is no problem from the processing result, it is determined in step a6 whether the same processing as above has been performed up to the data DN, and if No, execute the processing from step a1 onwards,
If the same process as above is performed up to the data DN, the process ends.

[Problems to be Solved by the Invention] However, in the conventional data storage method as described above, a memory area consisting of, for example, 8 bits is allocated and used for one piece of data, so the number of states is small. If an attempt is made to store a large amount of data that does not have a large amount of data, there is a problem that the memory area occupied increases with poor memory usage efficiency, and the processing time also increases proportionally.

- For example, if one storage area is 1 as shown above.
Considering a byte (8 bits) of memory, 256 states can be defined in one area, but in actual use, one data state can be defined in at most several types (
2 to 4).

Now, if we assume that there are four types of data states as shown in Figure 8, the storage area and end.

An area of 2 bits is sufficient, and an 8-bit configuration is not necessary. In other words, 6 bits are wasted per storage area, and overall, if there are N pieces of data, the used bits are 2N bits, but 6N bits (3 times as much) are wasted. It is a pit. Therefore, in such a conventional storage method, memory usage efficiency is poor, and the occupied memory area increases as the amount of data increases.

Furthermore, in the conventional storage method, when processing data, it is necessary to repeat the number of software steps required for this processing by the number N of occupied memory areas, and therefore, as the number of data increases, the processing time also increases. For example, if we consider a process in which process A is executed when data is in state 2 among all data, the algorithm at this time is as shown in FIG. That is, in this FIG. 10, in step b1, data is read, and in step b2, it is determined whether the data is roOJ (state ■), and if YE
If S, processing A is performed in step b3; if No, it is determined in step b4 whether data in all areas has been read; if NO, the process returns to step b1 again. Here, in the algorithm shown in FIG. 10, if each step number is set to 1 for simplicity, the number of steps required for the entire process is 3×N(
If the number of data is 512, the number of steps is 3×512=1536).

The present invention is an attempt to solve the above-mentioned problems, and is designed to use the memory area in a highly efficient manner when storing a plurality of N (N>2m) pieces of data with a number of states of 2m. At the same time, we were able to reduce data processing time. The purpose is to provide a data storage method.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In this FIG. 1, M1 to Mm are memories, and these memories M1 to Mm are set as a set, and each bit (1 to N) of each memory M1 to Mm has a maximum of 2m ways of state change. (N>2m) types of data D to DN are assigned and stored.

[Function] With this configuration, the state change mode can be changed up to 2m.
When storing data D1 to DN of (N>2111) types, each data D1 to D is allocated and stored for each bit (1 to N) of each memory M1 to Mm.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

This embodiment also concerns the method of storing data in the RAM of the data processing device using the CPU shown in FIG. 6, and FIG. 2 is a diagram showing one embodiment of the present invention. In Figure 2, Ml.

M2 is a memory area (save area) corresponding to addresses 1 and 2 of the RAM that stores data.These memory areas Ml and M2 are combined into a set, and each bit (1 to N) of each memory Ml and M2 is , the state change mode is up to 4 (2
m) There are N (N>2m) types of data D1 to DN.
is assigned and stored.

It is assumed that the CPU has the ability to simultaneously process N-bit data.

With the above configuration, when storing N types of data D to DN each having a maximum of 4 state change modes as described above, N bits are required to express all the states (2'' ways). Since it is sufficient to have two memory areas, two memory areas are prepared for two addresses, and each data D1 is stored for each bit (1 to N) of each memory area Ml, M2.
~ DN is assigned and stored.

In this way, there will be no wasted bits in the memory area, and therefore memory usage efficiency can be improved, and even if the number of data increases, the memory area occupied will be smaller than that of conventional methods. and does not increase.

In addition, in the single storage method, when processing data, it is only necessary to execute one software step required for this processing. For this reason, processing time can be shortened in proportion to the number of data. For example, if we consider a process in which process A is executed when data is in state I among all data, as in the previous example, then The algorithm is shown in Figure 3.

That is, in FIG. 3, in step A1, the data in memory area M1 is read at once, in step A2, the data in memory area M2 is read in all at once, and in step A3, the data in memory area M1 and M2 are read in at the same time. NOR the data stored in the bits, and in step A4 determine whether the result is "00" (state I). If No, perform process A in step A3; if YES, end. do. Here, in the algorithm shown in Fig. 3, if each step is set to 1 for simplicity, the number of steps required for the entire process is 4 if all states are other than ■, and the processing time is 1. It can be seen that the time is significantly shortened.

In general, when using k-bit memory and CPU, let N be the number of data with 2m states.
The required memory area is (N/k) x m bytes, which is N
>2m is smaller than the conventional N bytes.

Normally, compared to the number of data to be handled (for example, 512), m is at most about 2 to 4, so the same number of data as before can be stored in a smaller area than before.

Next, as a specific example, a case will be described in which a 1-byte (8-bit) memory is used and an 8-bit CPU capable of processing 8-bit data at a time is used as the CPU. In this case, it is assumed that the number of data is 512 and each data has four states.

Therefore, in this specific example, when storing 512 types of data, two memories are combined into a set,
Sixty-four of these memory pairs are prepared, and eight pieces of data are allocated and stored for each bit of each memory. That is, the fourth
As shown in the figure, data D1 to D are stored in memory area M
l-1, M2-1, and data D, ~D1. is memory area M1-2. Store it in M2-2 and do the same,
Divide the data into eight pieces, and the last data is D. ,
~D5□2 are stored in memory areas Ml-64 and M2-64.

In this way, 512 pieces of data with four states can be stored in 128 [(512/8)×2] bytes. On the other hand, since the conventional memory area occupied 512 bytes, according to the 1-bokuto method, the same amount of data can be stored in 1/4 the area.

When the memory area is reduced in this way, the hardware and the number of memory accesses are also reduced, which improves the processing power of the software.6 For example, as in the previous example, among all the data, data Considering a process in which process A is executed when is in state ■, the algorithm at this time is as shown in FIG. That is, in FIG. 5, in step B1, data in memory area M1 is read into 8 bits, and in step B2,
The data in the memory area M2 is read in 8 bits, and in step B3, the data in the memory area M1 is read.

NOR of the data stored in the corresponding bit of M2
In step B4, it is determined whether the result is [00" (state ■). If NO, step B5
Then, process A is performed, and if YES, it is determined in step B6 whether all areas have been read, and if NO, the process returns to step B1. Here, in the algorithm shown in Fig. 5, if the number of steps is set to 1 for simplicity, the number of steps required for the entire process is 5 x 64 = 320 steps when all states are other than 1, which is conventional The processing time can be reduced to about 115 compared to the 1536 steps in the case of .

The above has been explained using a specific example, but according to this method, C
If the number of bits that can be processed by the PU increases (from 8 bits to 16 bits) or the number of data increases, further improvement effects can be obtained.

[Effects of the Invention] As detailed above, according to the data storage method of the present invention, when storing N (N>2m) types of data each having a maximum of 2m states of change, m memories are used. Since the data is allocated and stored for each bit of each memory as a set, the memory area can be used with high memory usage efficiency and the data processing time can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. Figure 5 is a flowchart showing a processing algorithm in a concrete example of the present invention; Figure 6 is a block diagram of a data processing device; Figure 7 is a diagram explaining a storage area in RAM; FIG. 8 is a diagram showing the transition of the state of saved data, FIG. 9 is a flowchart showing an example of data processing in a data processing device, and FIG. 10 is a flowchart showing a processing algorithm in a conventional example. In the figure, 10 is an input port, and 11 is a CPU. 12 is a ROM, 13 is a RAM, 14 is an output port, and 15 is a pass line. Ml, M2. Ml-1, Ml-2, Ml-64, M2-
1. M2-2. M2-64. Mm and MNj are memories or memory areas (conservation work IJa). Mm N-1 N-1 Diagrams explaining the principles of the present invention M1 to Mm --- Memo, M1, M2 --- Memory area Diagrams showing the principles of the present invention 1077 Figure 6 M1~MN - 11 memo, storage area in the area RAM ti bright whistle figure! ! ■ Hard box ■ animal ■ m I'm dumbfounded, l5anjl@L (2) Figure 1st io Figure

Claims (1)

[Claims] There are a maximum of 2^m ways of changing the state N (N>2^m)
When storing each type of data (D_1-D_N), m memories (M1 to Mm) are combined into a set, and each memory (
A data storage method characterized in that the data is allocated and stored for each bit (M1 to Mm).