JPH0265255A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable an offset section to be large in breadth and to restrain a switching transistor from deteriorating in source-drain breakdown strength by a method wherein impurity is selectively introduced in an oblique direction against a substrate. CONSTITUTION:A gate electrode 9 is built on the gate insulating film of a switching transistor region and a peripheral transistor region. And, a side wall 11 is provided to the side of the gate electrode of the switching transistor region and the peripheral transistor region, and a resist film 5d is formed covering a peripheral transistor region 4b which includes the gate electrode 9 and the side wall 11. Then, As<+> is introduced in an oblique direction against a substrate 1 through, for instance, an As ion implantation method using the resist film 5d as a mask. By this setup, a drain diffusion layer 12a and a source diffusion layer 12b are formed so as to make the width of an offset section 10a on the drain side larger than that of an offset section 10b on the source side. Even if the side wall 11 becomes small in width with the integration, the width of the offset section 10a on the drain side can be larger than that of a conventional one, the source.drain breakdown strength can be prevented from deteriorating, and a phase can be safely cut off.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figure 4) Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems One Embodiment of the Present Invention (First Embodiment) Figures to Figure 3) Effects of the invention [Summary] Regarding the manufacturing method of semiconductor devices, it is possible to suppress the decrease in the source-drain breakdown voltage of the switching transistor that flows the current for blowing out the phase due to integration, and to reduce the phase The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can stably cut the semiconductor device. a step of forming a mask layer for forming a transistor region and a mask layer for forming a peripheral transistor region; a step of forming a field oxide film by selectively oxidizing the substrate using the mask layer as a mask; A step of exposing the substrate by selectively etching the mask layer and the insulating film and forming a switching transistor region and a peripheral transistor region, and removing the exposed substrate where the field oxide film is not formed. forming a gate insulating film in the switching transistor region and the peripheral transistor region by oxidation; forming a gate electrode on the gate insulating film in the switching transistor region and the peripheral transistor region; forming an offset portion made of a low concentration impurity region by selectively introducing impurities into the substrate of the switching transistor region and the peripheral transistor region; and the gate electrode of the switching transistor region and the peripheral transistor region. a step of forming a sidewall on a sidewall; a step of forming a mask layer for forming a first high concentration impurity region so as to cover a region of the peripheral transistor including the gate electrode and the sidewall; By selectively introducing impurities in an oblique direction to the substrate using the mask layer for forming a high concentration impurity region as a mask, the width of the offset portion on the drain side is made larger than the width of the offset portion on the source side. forming a source diffusion layer and a drain diffusion layer made of a first high-concentration impurity region so as to be large; and forming a second high-concentration impurity region so as to cover the switching transistor region including the gate electrode and the sidewall. forming a mask layer for forming a region, and selectively introducing impurities in a direction perpendicular to the substrate using the mask layer for forming the second high concentration impurity region as a mask; This method includes a step of forming a source diffusion layer and a drain diffusion layer consisting of a concentrated impurity region.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a semiconductor device, and more specifically, a switching method 1 in which a current flows to melt a phase.
-Regarding a method of manufacturing a semiconductor device that can prevent a decrease in the source train breakdown voltage of a random disk.

For example, semiconductor devices such as DRAMs that use redundant circuits have phase circuits to generate signals for controlling the redundant circuits, and by selectively blowing out the phases, the redundant circuits can be used. , switching from non-use to non-use is being carried out. The switching transistor that allows current to flow into this phase is LDD (Ligbtly Do
A MOSFET with a ped drain structure is used. In this case, the voltage to cut the phase is approximately 14
V is required.

[Conventional technology]

The conventional technology will be described below with reference to the drawings.

Fig. 4 is a diagram explaining a conventional method for manufacturing a semiconductor device, Fig. 5 is a cross-sectional view showing the structure of a conventional switching transistor and a phase, and Fig. 6 is an equivalent circuit diagram of a conventional switching transistor and a phase. be. The semiconductor device shown in FIG. 4 can be applied to a semiconductor device such as a DRAM, and the switching transistor constituting the DRAM is a MOS FET with an LDD structure.
For peripherals that make up RAM!・The transistor is a MOS FET with an LDD structure.

In these figures, 21 is made of, for example, Si and is, for example, a p-type substrate, 22a is a switching transistor region of a switching transistor through which a current for blowing out the phase flows, 22b is a peripheral transistor region, 23 is a channel stopper, and 24 is a For example, a field oxide film made of SiO□, 25 a gate insulating film made of SiOz, 26 a gate electrode made of polysilicon, 27 an offset part made of a low-concentration impurity region, and 28 a n 29 is a side wall made of, for example, 5102; 30 is an interlayer insulating film made of, for example, PSG;
31 is a contact hole, 32 is a wiring layer made of, for example, Aβ, 33 is a cover film made of, for example, 5in2, 34 is an insulating film made of, for example, 5i02, 35 is a phase made of, for example, polysilicon, and 36 is a layer for fusing the phase 35. It is a switching transistor that allows current to flow.

The LDD structure is composed of an offset portion 27 made of a lightly doped region and a source/drain diffusion layer 28 made of a heavily doped region.

Next, the principle of operation will be briefly explained using FIGS. 5 and 6.

A semiconductor device using a redundant circuit as shown in FIGS. 5 and 6 has a phase 35 circuit to generate a signal for controlling the redundant circuit, and the phase 35 is selectively blown out. By doing this, you can switch between using and not using the redundant circuit.

Next, the manufacturing method will be briefly explained.

As shown in FIG. 4, the switching transistor 36 and peripheral transistors are MOS FETs with the same structure.
The manufacturing methods for both were exactly the same. In particular, the switching transistor 36
The offset portion 27 and the source/drain diffusion layer 28, which constitute the peripheral transistor's DD tank structure, are formed by a commonly used ion implantation method in a direction perpendicular to the substrate 1.

[Problem to be solved by the invention]

However, in such conventional semiconductor device manufacturing methods, as the gate insulating film 25 becomes thinner and the width of the sidewall 29 on the side wall of the gate electrode 26 becomes narrower, the L of the switching transistor becomes thinner. D D
As the width of the offset portion 27 forming the structure becomes narrower, the source and drain breakdown voltage of the switching transistor decreases.
12-14V typically required to cut the fuse
Breakdown is likely to occur even at a voltage of

Here, when the width of the sidewall 29 becomes narrower, the width of the offset portion 27 becomes narrower because the width of the sidewall 29 becomes narrower.
When the width of the offset portion 27 becomes narrower, the width of the offset portion 27 becomes smaller as shown in FIG.
As shown in FIG. 7(b), the area becomes narrower as if the portion absorbed by the source/drain diffusion layer 28 increases, and this is because the formation of the source/drain diffusion layer 28 is normally performed. This is thought to be due to the vertical ion implantation method. The reduction in the source-drain breakdown voltage of the switching transistor is particularly caused by the width of the offset portion 27 on the drain side of the switching transistor becoming small.

Therefore, the present invention provides a method for manufacturing a semiconductor device that is capable of suppressing a decrease in the source train breakdown voltage of a switching transistor through which a current flows to fuse a phase due to integration, and that can stably disconnect a phase. It is intended to.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes the steps of sequentially forming an insulating film and an oxidation-resistant film on a substrate;
A step of forming a mask layer for forming a switching transistor region and a mask layer for forming a peripheral transistor region by selectively etching the oxidation-resistant film; and a step of selectively etching the substrate using the mask layer as a mask. forming a field oxide film by oxidizing;
selectively etching the mask layer and the insulating film to expose the substrate and forming a switching transistor region and a peripheral transistor region; and the exposed substrate on which the field oxide film is not formed. forming a gate insulating film in the switching transistor region and the peripheral transistor region by oxidizing the gate electrode; forming a gate electrode on the gate insulating film in the switching transistor region and the peripheral transistor region; forming an offset portion made of a low concentration impurity region by selectively introducing impurities into the substrate of the switching transistor region and the peripheral transistor region; and the gate of the switching transistor region and the peripheral transistor region. a step of forming a sidewall on a side wall of the electrode; a step of forming a mask layer for forming a first high concentration impurity region so as to cover a region of the peripheral transistor including the gate electrode and the sidewall; By selectively introducing impurities in an oblique direction to the substrate using the mask layer for forming the high concentration impurity region of No. 1 as a mask, the width of the offset portion on the drain side is made larger than the width of the offset portion on the source side. forming a source diffusion layer and a drain diffusion layer made of a first high-concentration impurity region such that the area is large; and forming a second high-concentration impurity region so as to cover the switching transistor region including the gate electrode and the sidewall. forming a mask layer for forming a region, and selectively introducing impurities in a direction perpendicular to the substrate using the mask layer for forming the second high concentration impurity region as a mask; This method includes a step of forming a source diffusion layer and a drain diffusion layer consisting of a concentrated impurity region.

[Effect]

In the present invention, an insulating film and an oxidation-resistant film are sequentially formed on a substrate,
After a mask layer for forming a switching transistor region and a mask layer for forming a peripheral transistor region are formed by selectively etching the oxidation-resistant film, a field oxide film is formed by selectively oxidizing the substrate using the mask layer as a mask. is formed. Next, the mask layer and the insulating film are selectively etched to expose the substrate, a switching transistor region and a peripheral transistor region are formed, and the exposed substrate on which no field oxide film is formed is oxidized to perform switching. After a gate insulating film is formed in the transistor region and the peripheral transistor region, a gate electrode is formed on the gate insulating film in the switching transistor region and the peripheral transistor region.

Next, impurities are selectively introduced into the substrate of the switching transistor region and the peripheral transistor region, thereby forming an offset portion made of a low concentration impurity region, and forming a side wall on the side wall of the gate electrode of the switching transistor region and the peripheral transistor region. After this is formed, a mask layer for forming a first high concentration impurity region is formed so as to cover the peripheral transistor region including the gate electrode and sidewalls. Next, using the first mask layer for forming a high concentration impurity region as a mask, impurities are selectively introduced diagonally to the substrate, so that the width of the offset portion on the drain side becomes the width of the offset portion on the source side. A source diffusion layer and a drain diffusion layer made of the first high-concentration impurity region are formed so as to be larger than that of the second high-concentration impurity region, and a second high-concentration impurity region is formed so as to cover the switching transistor region including the gate electrode and sidewalls. After the mask layer for forming the second high concentration impurity region is formed, impurities are selectively introduced in the direction perpendicular to the substrate using the mask layer for forming the second high concentration impurity region as a mask. A source diffusion layer and a drain diffusion layer are formed.

Therefore, even if the width of the sidewall becomes narrower due to integration, the width of the offset part on the drain side of the switching transistor can be made larger than when using the conventional vertical ion implantation method. This makes it possible to suppress the drop in the source/drain breakdown voltage of the transistor, making it possible to stably cut the phase.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIGS. Figure 2 (a), (b)
) is a diagram showing the details of the LDD structure of the switching transistor of one embodiment, and FIGS. 3(a) and 3(b) are diagrams showing the details of the LDD structure of the peripheral transistor of one embodiment.

In addition, FIG. 2(a) and FIG. 3(a) are plan views,
FIG. 2(b) and FIG. 3(b) are cross-sectional views.

In these figures, 1 is a p-type substrate made of, for example, St, and 2 is an insulating film made of, for example, SiO□, which is also called a pad 5 iOz film. 3 is an oxidation-resistant film made of, for example, Si or N4; 3a, 3b are mask layers; 4a is a switching transistor region of a switching transistor through which a current flows to melt the phase; 4b is a peripheral transistor region; 5a, 5b, 5c; 5d and 5e are resist films; 6a, 6b, and 6c are channel stoppers; 7 is a field oxide film made of, for example, SiOz; 8 is a gate insulating film made of, for example, SiO□; 9 is a gate electrode made of, for example, polysilicon; 10a , 10b.

Reference numeral 10c is an n-type offset portion made of a low concentration impurity region, and offset portion 10a is an offset portion on the drain side of the switching transistor.
b is an offset portion on the source side of the switching transistor, and offset 10c is an offset portion of the peripheral transistor. 11 is a side wall made of, for example, SiO□; 12a is an n-type drain diffusion layer made of a first high-concentration impurity region; 12b is an n-type source diffusion layer made of a first high-concentration impurity region; 12c is a sidewall made of SiO□; An n-type source/drain diffusion layer made of a second high-concentration impurity region, 13 a glabellar insulating film made of, for example, PSG, 14 a contact hole, and 15, for example, A! A wiring layer consisting of 1
6 is a cover film made of, for example, PSG.

Note that the mask layer 3a is the switching transistor region 4.
The mask layer 3b is a mask layer for forming the peripheral transistor region 4b. The LDD structure of the switching transistor has offset parts 10a, 1
0b, a drain diffusion layer 12a, and a source diffusion layer 12b, and the LDD structure of the peripheral transistor includes an offset portion 10C and a source/drain diffusion layer 12c.

Next, the manufacturing method will be explained.

First, as shown in FIG. 1(a), an insulating film 2 is formed on a substrate 1 by, for example, a thermal oxidation method, and then Si3N is deposited on the insulating film 2 by, for example, a CVD method to form an oxidation-resistant film 3. Form. This corresponds to the step of sequentially forming an insulating film and an oxidation-resistant film on a substrate according to the present invention.

Next, as shown in FIG. 1(b), mask layers 3a and 3b are formed by selectively etching the oxidation-resistant film 3 by, for example, RIE. At this time, the mask layer 3a is patterned so that only the switching transistor region 4a and the mask layer 3b are patterned so that only the peripheral transistor region 4b remains. This corresponds to the step of forming a mask layer for forming a switching transistor region and a mask layer for forming a peripheral transistor region by selectively etching the oxidation-resistant film of the present invention.

Next, after forming a resist film 5a to cover the mask layer 3a, the resist film 5a is formed by, for example, B ion implantation.
Channel stoppers 6a, 6b,
Form 6c. At this time, channel stoppers 6a and 6b
is formed apart from the switching transistor region 4a.

Next, as shown in FIG. 1C, after removing the resist film 5a, a field oxide film 7 is formed by selectively oxidizing the substrate 1 by field oxidation using the mask layers 3a and 3b as a mask. .

This corresponds to the step of forming a field oxide film by selectively oxidizing the substrate according to the present invention.

Next, as shown in FIG. 1(d), after all of the mask layers 3a and 3b are selectively removed by wet etching using, for example, a phosphoric acid solution, the field oxide film 7 and the insulating film are removed by wet etching using, for example, a hydrofluoric acid solution. The film 2 is selectively etched to form a switching transistor region 4a and a peripheral transistor region 4b. At this time, the substrate 1 is exposed. This corresponds to the step of exposing the substrate and forming the switching transistor region and the peripheral transistor region of the present invention.

Next, as shown in FIG. 1(e), by oxidizing the exposed substrate 1 on which the field oxide film 7 is not formed, for example, by thermal oxidation, gates are formed in the switching transistor region 4a and the peripheral transistor region 4b. An insulating film 8 is formed. This corresponds to the step of forming the gate insulating film by oxidizing the substrate in the present invention. Then,
An impurity such as B for controlling the surface concentration is selectively introduced into the channel portions of the switching transistor region 4a and the peripheral transistor region 4b.

Next, as shown in FIG. 1(f), polysilicon is deposited over the entire surface by, for example, the CVD method so as to cover the switching transistor region 4a and the peripheral transistor region 4b, and then unnecessary polysilicon is deposited by, for example, the RIE method. A gate electrode 9 is formed on the gate insulating film 8 in the switching transistor region 4a and the peripheral transistor region 4b by selectively etching the portion. This corresponds to the step of forming the gate electrode of the present invention.

Next, as shown in FIG. 1(g), a resist film 5 is formed so as to cover the peripheral transistor region 4b including the gate electrode 9.
After forming P, for example, P' is selectively introduced into the substrate 1 in the switching transistor region 4a using the resist film 5b and the gate electrode 9 as a mask by ion implantation, thereby forming offset portions 10a and 10b.

Next, as shown in FIG. 1H, after removing the resist film 5b and forming a resist film 5C so as to cover the switching transistor region 4a including the gate electrode 9, the resist film 5C is formed by, for example, P ion implantation. The offset portion 10c is formed by selectively introducing P+ into the substrate 1 in the peripheral transistor region 4b using the film 5c' and the gate electrode 9 as a mask. The steps shown in FIG. 1(g) and FIG. 1(h) of the present invention form an offset portion consisting of a low concentration impurity region by selectively introducing impurities into the substrate of the switching transistor region and the peripheral transistor region. This corresponds to the process of forming.

Next, as shown in FIG. 1(i), the resist film 5c was removed, and SiO□ was deposited on the entire surface by, for example, the CVD method so as to cover the gate electrode 9 of the switching transistor region 4a and the peripheral transistor region 4b. After, for example, R
A sidewall 11 is formed on the side wall of the gate electrode 9 in the switching transistor region 4a and the peripheral transistor region 4b by selectively etching unnecessary portions of 5 in 2 using the IE method. This corresponds to the step of forming side walls on the side walls of the gate electrodes in the switching transistor region and the peripheral transistor region according to the present invention.

Next, as shown in FIG. 1N, a resist film 5 for forming a first high concentration impurity region is formed so as to cover the peripheral transistor region 4b including the gate electrode 9 and the sidewall 11.
form d. This corresponds to the step of forming a mask layer for forming the first high concentration impurity region according to the present invention. Next, by introducing As'' into the substrate 1 in a diagonal direction using the resist film 5d as a mask by, for example, an ion implantation method of As, the width of the offset 1 part 10a on the drain side is changed to the width of the offset 1 part 10b on the source side. The train diffusion layer 12a and the source diffusion layer 12b are formed so that their width is larger than the width of the transistor.The oblique ion implantation is performed so that the gate electrode 9 and the sidewall 11 of the switching I/transistor are oriented in the same direction. This corresponds to the step of forming the source diffusion layer and drain diffusion layer made of the first high concentration impurity region of the present invention.

Next, as shown in FIG. 1(k), a resist film 5e for forming a second high concentration impurity region is formed so as to cover the switching transistor region 4a including the gate electrode 9 and the sidewall 11. This corresponds to the step of forming a mask layer for forming the second high concentration impurity region according to the present invention. Next, the source/drain diffusion layer 12c is formed by introducing As'' in a direction perpendicular to the substrate 1 using the resist film 5e as a mask using a commonly used ion implantation method for As. , corresponds to the step of forming a source diffusion layer and a drain diffusion layer consisting of the second high concentration impurity region.

Next, as shown in FIG. 1(ff), after forming an interlayer insulating film 13, a contact hole 14 is formed in the interlayer insulating film 13. Then, after forming the wiring layer 15 so as to make contact with each electrode through the contact hole 14,
By forming the cover film 16 to cover the entire surface,
A semiconductor device having a structure as shown in FIG. 1 is completed.

That is, in the above embodiment, as shown in FIG. 1(j), for example, As''
By selectively introducing , the width (
A) shown in FIG. 2(a) is off-cellar I/section 1 on the source side.
Since the drain diffusion layer 12a and the source diffusion layer 12b are formed to be larger than the width of the sidewall 0b (B shown in FIG. 2(a) 4), even if the width of the sidewall 11 becomes smaller due to integration, The width of the offset portion 10a on the drain side of the switching transistor can be made larger than that obtained by conventional vertical ion implantation, and a decrease in the source/drain breakdown voltage of the switching transistor can be suppressed, and the phase can be cut stably. Can be done. Note that although the width of the offset portion 10b on the source side is smaller than in the conventional vertical ion implantation method, there is an advantage that a large amount of current can be obtained.

Furthermore, it is conceivable that the source/drain breakdown voltage may decrease as the substrate concentration increases and the channel dose increases, but this can be suppressed by making the width of the offset portion 10a on the drain side sufficiently large.

〔effect〕

According to the present invention, it is possible to suppress a decrease in the source/drain breakdown voltage of a switching transistor through which a current for cutting a phase flows due to integration, and it is possible to stably cut a phase.

[Brief explanation of the drawing]

1 to 3 are diagrams for explaining an embodiment of the method for manufacturing a yt'-conductor device according to the present invention, FIG. 1 is a diagram for explaining the method for manufacturing one embodiment, and FIG. FIG. 3 is a diagram showing details of the LDD structure of the peripheral transistor of one embodiment; FIG. 4 is a diagram explaining a conventional example; The figure is a cross-sectional view showing the structure of a conventional switching transistor and a phase, FIG. 6 is an equivalent circuit diagram of a conventional switching transistor and a phase, and FIG. 7 is a diagram explaining problems with the conventional example. ...Substrate, ...Insulating film, ...Oxidation-resistant film, a...Switching transistor region, b...
...Peripheral transistor area, 6a, 6b, 6c.
...Channel stopper, 7...Field oxide film, 8...Gate insulating film, 9...Gate electrode, 10a, 10b, 10c...・Offset part, 1
1...Side wall, 12a...Drain diffusion layer, 12b...Source diffusion layer, 12c...Source/drain diffusion layer, 13...
...Interlayer insulating film, 14...Contact hole, 15...Wiring layer, 16...Cover film. Ward

Claims (1)

[Claims] A method for manufacturing a semiconductor device including a phase and a switching transistor that flows a current for melting the phase, comprising the steps of: sequentially forming an insulating film and an oxidation-resistant film on a substrate; forming a mask layer for forming the switching transistor region and a mask layer for forming the peripheral transistor region by selectively etching the film; selectively oxidizing the substrate using the mask layer as a mask; forming a field oxide film by selectively etching the mask layer and the insulating film to expose the substrate and forming a switching transistor region and a peripheral transistor region; a step of forming a gate insulating film in the switching transistor region and the peripheral transistor region by oxidizing the exposed substrate on which no film is formed; and a step of forming a gate insulating film in the switching transistor region and the peripheral transistor region. a step of forming a gate electrode on the film; a step of selectively introducing impurities into the substrate of the switching transistor region and the peripheral transistor region to form an offset portion consisting of a low concentration impurity region; forming a sidewall on the sidewall of the gate electrode of the transistor region and the peripheral transistor region; and forming a first high concentration impurity region so as to cover the peripheral transistor region including the gate electrode and the sidewall. a step of forming a mask layer, and using the mask layer for forming the first high concentration impurity region as a mask, selectively introducing impurities in an oblique direction with respect to the substrate, thereby changing the width of the offset portion on the drain side; forming a source diffusion layer and a drain diffusion layer made of a first high concentration impurity region such that the width of the offset portion is larger than the width of the offset portion on the source side; and the switching transistor region including the gate electrode and the sidewall. forming a second mask layer for forming a high concentration impurity region so as to cover the second high concentration impurity region; and selecting impurities in a direction perpendicular to the substrate using the second mask layer for forming a high concentration impurity region as a mask. 1. A method of manufacturing a semiconductor device, comprising the step of forming a source diffusion layer and a drain diffusion layer made of a second high-concentration impurity region by introducing a second high-concentration impurity region.