JPH0265340U - - Google Patents
Info
- Publication number
- JPH0265340U JPH0265340U JP1988145033U JP14503388U JPH0265340U JP H0265340 U JPH0265340 U JP H0265340U JP 1988145033 U JP1988145033 U JP 1988145033U JP 14503388 U JP14503388 U JP 14503388U JP H0265340 U JPH0265340 U JP H0265340U
- Authority
- JP
- Japan
- Prior art keywords
- header
- semiconductor chip
- electrode pads
- power supply
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Semiconductor Memories (AREA)
Description
第１図および第２図は本考案に依る半導体装置
を説明する上面図および断面図、第３図および第
４図は従来の半導体装置を説明する上面図および
断面図である。
を説明する上面図および断面図、第３図および第
４図は従来の半導体装置を説明する上面図および
断面図である。
Claims (1)
- 【実用新案登録請求の範囲】 (1) 複数の電極パツドを有する半導体チツプと
前記半導体チツプを載置するヘツダーと前記ヘツ
ダーに隣接し且つ前記電極パツドとボンデイング
ワイヤにより接続された複数のリードとを有する
半導体装置において、前記ヘツダーを２分割し、
前記ヘツダー上に設けた絶縁層を介して前記半導
体チツプを載置し、前記半導体チツプ上の異なる
電源端子となる前記電極パツドと前記夫々のヘツ
ダーとをボンデイングワイヤで接続して電源配線
と兼用することを特徴とした半導体装置。 (2) 前記半導体チツプとしてダイナミツクラン
ダムアクセスメモリを用い、前記半導体チツプ上
の両側に異なる種類の同一の電源端子の前記電極
パツドを設け、前記同一の電源端子の電極パツド
をボンデイングワイヤにより夫々の近くの２分割
した前記ヘツダーに接続することを特徴とした請
求項１記載の半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988145033U JPH0265340U (ja) | 1988-11-07 | 1988-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988145033U JPH0265340U (ja) | 1988-11-07 | 1988-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0265340U true JPH0265340U (ja) | 1990-05-16 |
Family
ID=31413267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988145033U Pending JPH0265340U (ja) | 1988-11-07 | 1988-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0265340U (ja) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62283635A (ja) * | 1986-05-31 | 1987-12-09 | Toshiba Corp | 半導体装置 |
-
1988
- 1988-11-07 JP JP1988145033U patent/JPH0265340U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62283635A (ja) * | 1986-05-31 | 1987-12-09 | Toshiba Corp | 半導体装置 |