JPH026659Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an AM detection circuit that synchronously detects AM signals, and in particular, an interference elimination type AM detection circuit that is equipped with a circuit that eliminates beat interference caused by adjacent waves. Regarding.

[Conventional technology]

Figure 2 shows a conventional interference elimination type AM detection circuit.
is an AM signal input terminal, and 2 is a synchronous detector.
A so-called PLL circuit is composed of a phase detector 3, a low-pass filter 4, a voltage controlled oscillator 5, and a frequency divider 6. 7 is a 90° phase shifter, 8 is an adder/subtractor that performs addition or subtraction, and 9 is an output terminal.

A desired signal Dcosω ₁ t and an adjacent interference signal Ucosω ₂ t are input to the input terminal 1 . In the PLL circuit, in response to the carrier wave cosω ₁ t of the desired signal, a reproduction carrier wave cosω ₁ t and sinω ₁ t are outputted from a frequency divider 6 and applied to a synchronous detector 2 and a phase detector 3, respectively. Therefore, the following multiplications are performed in the synchronous detector 2 and the phase detector 3, respectively.

(Dcosω ₁ t+Ucosω ₂ t)cosω ₁ t…(1) (Dcosω ₁ t+Ucosω ₂ t)sinω ₁ t…(2) The multiplication results are respectively D/2(1+cos2ω ₁ t)+U/2{cos(ω ₁ − _ω2 )
t+cos(ω ₁ +ω ₂ )t} …(3) D/2(sin2ω ₁ t)+U/2{sin(ω ₁ −ω ₂ )t+
sin(ω ₁ +ω ₂ )t} …(4). When the synchronous detector 2 and the phase detector 3 remove and output the frequency components of (ω ₁ +ω ₂ ) and 2ω ₁ from the signal in the above equation, the synchronous detector 2 outputs D/2+U/2{cos (ω ₁ −ω ₂ )t}…(5) The phase detector 3 outputs U/2{sin(ω ₁ −ω ₂ )t}…(6). In the signals of equations (5) and (6), D/2 is the desired signal and the others are interference beat signals. The phase difference between the beat signals in equations (5) and (6) is 90°, but the signal in equation (6) is phase-shifted by 90° in the phase shifter 7, so -U/2{cos(ω ₁ −ω ₂ )t} (7), and when ω ₁ >ω ₂ , beat signals having a negative phase relationship are input to the adder/subtractor 8 . In this case, the adder/subtracter 8 adds the signals of equations (5) and (7), so the beat signal is canceled and the desired signal D/2 is added.
is output to the output terminal 9. When ω ₁ <ω ₂ , the beat signals input to the adder/subtracter 8 are in phase, so the adder/subtracter 7 performs subtraction and cancels the beat signal.

[Problem that the invention attempts to solve]

When converting a PLL circuit into an IC, the frequency divider consists of multiple stages of flip-flops. FIG. 3 is an example of this. Since the frequency is divided by 1/2 in one flip-flop stage, in this case the voltage controlled oscillator 5 oscillates at a frequency four times that of the carrier wave. Divide the output of voltage controlled oscillator 5 into 1/2 using flip-flop _F1 , add the output Q to flip-flop _F2 , add the output Q with the opposite phase to flip-flop _F3 , and divide the frequency into 1/2. . Thus, the reproduction carrier waves cosω ₁ t and sinω ₁ t
can be obtained. The reproduction carrier wave sinω ₁ t is PLL
The input AM signal is a signal within the loop of the circuit.
It has a phase difference of exactly 90° with the carrier wave of Dcosω ₁ t. However, due to the delay in the operation of the flip-flop in the frequency divider 6, the phase difference between the regenerating carrier wave applied to the synchronous detector 2 and sinω ₁ t is not 90°, and a slight delay θ occurs, resulting in cos(ω ₁ t− θ). Therefore, the multiplication performed by the phase detector 3 remains as in equation (2), but the multiplication performed by the synchronous detector 2 is (Dcosω ₁ t+Ucosω ₂ t)cos(ω ₁ t−θ)...(8 ) becomes. As a result, the synchronous detector 2 removes harmonics.
The output of is Dcosθ/2+Ucosθ/2{cos(ω ₁ −ω ₂ t}+
Usin θ/2 {sin (ω ₁ −ω ₂ t} ) (9), and two orthogonal beat signals are generated.
The beat signal in the second term of the signal in equation (9) can be eliminated by the conventional circuit shown in Figure 2 by adjusting the level, but the beat signal in the third term is output. There's a problem.

As mentioned above, this invention uses the delay in the operation of the frequency divider to combine the regenerative carrier wave and the input signal to the synchronous detector 2.
It is an object of the present invention to provide an interference elimination type AM detection circuit including a circuit that also eliminates the beat signal component of the third term in equation (9) that occurs when there is a phase difference θ between the AM signal and the carrier wave.

[Means to solve the problem]

The beat signal component in the third term of equation (9) that occurs when the regenerating carrier wave applied to the synchronous detector 2 is cos(ω ₁ t−θ) is in phase with the beat signal output from the phase detector 3. Focusing on the synchronous detector 2
Means for adding or subtracting the output of the phase detector 3 and the output of the phase detector 3 is provided.

〔Example〕

FIG. 1 shows an embodiment of the interference-eliminating AM detection circuit of the present invention. Components in FIG. 1 that are the same as those in FIG. 2 are given the same symbols and their explanations will be omitted. The difference between FIG. 1 and FIG. 2 is that a first adder/subtractor 10 is added. Note that the adder/subtracter 8 is replaced by the second adder/subtracter 8.
And so.

If the regenerating carrier wave applied to the synchronous detector 2 is cos(ω ₁ t−θ), the output of the synchronous detector 2 is Dcosθ/2 + Ucosθ/2{cos(ω ₁ −ω ₂ )t in equation (9). } +Usinθ/2{sin(ω ₁ −ω ₂ )t} (10). In addition, since the regenerating carrier wave added to the phase detector 3 is a signal within the loop of the PLL circuit, the input
It is sinω ₁ t with a 90° phase difference from the carrier wave of the AM signal. Therefore, the output of the phase detector 3 is U/2{sin(ω ₁ −ω ₂ )t} (11) in equation (6). In the first adder/subtractor 10, the signal of equation (10) and the signal obtained by multiplying the signal of equation (11) by sinθ are subtracted from each other. Therefore, the first adder/subtractor cancels the beat signal in the third term of equation (10) and outputs Dcosθ/2 Ucosθ/2{cos(ω ₁ −ω ₂ )t}...(12) Ru. The signal of equation (11) is phase-shifted by 90 degrees by the phase shifter 7, and becomes −U/2{cos(ω ₁ −ω ₂ )t} (13). In the second adder/subtractor 8, the signal of equation (12) and
The signal obtained by multiplying the signal in equation (13) by conθ is added together. Therefore, the second adder/subtractor 8 cancels the beat signal in the second term of equation (12) and outputs only the desired signal Dcosθ/2. Above, ω ₁ ＞
In the case of ω ₂ , if ω ₁ <ω ₂ , the addition and subtraction of the first and second adders/subtracters are reversed and the beat signal is canceled.

[Effect of idea]

In the interference elimination type AM detection circuit of the present invention, since the first and second adders/subtracters are provided to remove both of the two orthogonal beat signals, the position of the reproduced carrier wave added to the synchronous detector and the phase detector is Beat signals caused by a phase difference of more than 90° can also be eliminated.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the interference eliminating type AM detection circuit of the present invention, FIG. 2 shows a conventional example, and FIG. 3 shows a detailed diagram of a frequency divider. 2... Synchronous detector, 3... Phase detector, 4...
Low-pass filter, 5... Voltage controlled oscillator, 6... Frequency divider, 7... Phase shifter, 8... Second adder/subtractor, 1
0...first adder/subtractor, 3-6...PLL circuit.

Claims (1)

[Claims for Utility Model Registration] a. A synchronous detector that synchronously detects an AM signal. b. A PLL circuit that includes a phase detector, a low-pass filter, a voltage controlled oscillator, and a frequency divider and responds to the carrier wave of the AM signal. c. A phase shifter d that shifts the phase of the output of the phase detector by 90 degrees. A first adder/subtractor e that adds or subtracts the output of the synchronous detector and the output of the phase detector. The output of the first adder/subtractor and the A second adder/subtractor that adds or subtracts the output from the phase shifter.An interference-eliminating AM detection circuit consisting of each of the above items.