JPH0267008A - Pll circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to phase locked loop (PLL) circuits.

[Conventional technology]

A conventional PLL circuit consists of a voltage controlled oscillator (VCO), a phase comparator, a charge pump, and a loop filter (low-pass filter) as basic elements.
An example is one in which 0 and voltage follower 4 are eliminated. A more advanced PLL circuit is
021, which has a plurality of phase comparators and loop filters, and has a judgment circuit that switches the phase comparators and loop filters according to the internal state of the PLL circuit is known.

[Problems to be Solved by the Invention] However, in the prior art described above, the VCO used in the integrated circuit PLL circuit is often of the CR multi-vibration type, so it is less efficient than the LC oscillation type or resonator oscillation type VCO. The phase fluctuation (jitter) of the VCO output with respect to the input signal was large. The lock range that provides the minimum jitter is
The band was extremely narrow.

SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a PLL circuit with a small number of parts, low jitter, and a wide lock range.

[Means for Solving the Problems] The PLL circuit of the present invention uses a phase comparator to detect a phase difference between a human input signal and a comparison input sourced from a voltage controlled oscillator, and opens and closes a charge pump output based on the detected information. A PLL circuit that converts the voltage into a voltage and supplies it to the voltage controlled oscillator through a loop filter to control its oscillation frequency is characterized by having the following configuration.

a) Voltage buffer means which receives as input the output voltage of the loop filter and has a time constant circuit consisting of a resistance and a capacitance.

b) Feedback means for feeding the output of the voltage buffer means to a connection point between a capacitance and a resistance of the loop filter.

[Function] According to the above configuration of the present invention, when the charge pump is turned on during locking, negative feedback is applied to the low-pass filter for the response time of the voltage follower, which works to suppress potential fluctuations at the output of the low-pass filter. Therefore, the input voltage fluctuation of the VCO is reduced and jitter is reduced.

[Embodiment 1] FIG. 1 is an example of a PLL circuit in an embodiment of the present invention. In FIG. Compare the frequency and phase of the comparison human power 24 divided by , and when the phase is leading, D = "H", and when the phase is lagging, tJ = "H".
” which operates equivalent to that shown in US Patent No. 3610954.
When the signal input 23 and the comparison input 24 do not match, the charge pump 2 with the 8-configuration turns on either the P-channel transistor 13 or the N-channel transistor 14 to supply charge to the low-pass filter indicated by the broken line frame 3. It is a kind of D/A converter. The low-pass filter 3 is a lug hood filter composed of a resistor 7.8 and a capacitor 9. The output 26 of the low-pass filter is buffered by the voltage follower 4 and connected to the input of the VCO 5. Voltage follower 4
is inserted in order to change the oscillation frequency range of the VCO by the variable resistor 22, and is not essential in the present invention. It is fed back to node 21 of the low pass filter.

Now, when the PLL circuit shown in Figure 1 is locked, the output 24 of the charge pump is not a digital waveform as shown in waveform 25 of Figure 2, but the peak value does not swing up to the power supply, and the waveform becomes a spike-shaped triangular wave. . As the lock state of the PLL circuit progresses, the charge injected from the charge pump becomes infinitely zero.
Ideally, it would be close to , but in actual circuits it does not go below a finite value due to delay in response of the phase comparator and vCO, unbalance of charge pump output capacity, etc. Therefore, the input voltage of vCO is not ideal. Since the voltage moves back and forth within a certain range around the voltage, jitter occurs, which is a phenomenon in which the output (phase, frequency) of the VCO fluctuates. Therefore, in order to reduce sick, it is sufficient to reduce the fluctuation of the vCO input terminal during locking.

Therefore, in the present invention, a voltage follower 4 is placed between the VCO and the low-pass filter, the output of the voltage follower 4 is fed back to the low-pass filter 3, and a resistor 10 is provided as a means for suppressing voltage fluctuations in the low-pass filter output.

Resistor 10 reduces the voltage fluctuation of the low pass filter when locked. In other words, when the charge pump output 25 has high impedance, the resistor 10 acts as a voltage follower 1.
2 input and output, low-pass filter node 21.25
are at the same potential, so that the charge of the capacitor 9 is compensated so that the charge is not lost due to leakage current or noise. On the other hand, when the charge bomb output is turned on, the output 22 of the voltage follower becomes thick (
Works in a direction that does not change. When the output of the charge pump 2 is turned on, the resistor 10 acts to reduce fluctuations in the output voltage of the low-pass filter 3. In other words, during the time from when the charge pump is turned on until the output of the voltage follower 4 changes, the resistor 10 feeds back the potential just before the charge pump was turned on to the capacitor 9, so it acts to prevent the potential at the node 21 from changing. do. Therefore, the value of resistor 10 can be changed to low bass fill 3 or voltage follower 4.
If you optimize it to the extent that it does not affect the basic operation of
Since the input voltage of the VCO is stabilized, jitter can be significantly reduced. In fact, using a CR multi-by-break type VCO, the input frequency is 16KHz, ■C
When a PLL circuit with an oscillation frequency of 2 MHz was configured,
The jitter was reduced to 1/10 (±10 ns) compared to the conventional circuit. Furthermore, it was observed that the lock range was expanded several times.

Figure 3 shows that the present invention is applicable not only to lag-lead filters but also to other loop filters, and that the voltage follower that applies feedback can be placed outside the loop of the PLL circuit to apply feedback to the loop filter. In Figure 0, which shows that the object of the invention can be achieved, the low-pass filter 5 includes an inverter 16, a resistor 8, and a capacitor 9.
This is an active filter consisting of In FIG. 3, the output of the low-pass filter 5 is used as the input of the VCO, but it goes without saying that the object of the present invention can also be achieved with a configuration in which the output of the voltage follower is used as the input of the VCO.

[Effects of the Invention 1] As described above, according to the present invention, the following effects are achieved by applying feedback from the voltage follower to the low-pass filter using only a resistor.

a) It is possible to significantly reduce jitter during locking and realize a highly stable PLL circuit.

b) PLL circuit stability and lock-up time are contradictory characteristics, but PLL circuit has high stability and fast lock-up time.
LL circuit can be realized.

C) An easy-to-use PLL circuit with a wide lock range can be realized.

9... Capacitor 12...Operation amplifier 15.16...In Park

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the PLL circuit of the present invention. FIG. 2 is a diagram showing the operation timing of the PLL circuit of FIG. 1. FIG. 3 is a diagram showing another embodiment of the present invention. Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Masataka Ueyanagi (1 other person) 1...
... Phase comparator 2 ... Charge pump 3 ... Loop filter (low pass filter) 4 ... Voltage follower 5 ... Voltage controlled oscillator 6 ... ... Frequency divider 7.8.10.11 ... Resistor "Hi-2,

Claims (1)

[Claims] The phase difference between the input signal and the comparison input sourced from the voltage controlled oscillator is detected by a phase comparator, the charge pump output is opened or closed based on the detected information to convert the voltage, and the voltage is passed through the loop filter. A PLL circuit configured to supply a signal to a controlled oscillator to control its oscillation frequency, the PLL circuit having the following configuration. a) Voltage buffer means which receives as input the output voltage of the loop filter and has a time constant circuit consisting of a resistance and a capacitance. b) Feedback means for applying the output of the voltage buffer means to a connection point between a capacitance and a resistance of the loop filter.