JPH0267045A - Packet switch - Google Patents

Abstract

PURPOSE:To respond to the housing of an ultra fast line and the increment of the number of lines by operating in parallel plural subswitches to switch the plural bits of a serial-parallel converted packet signal, and parallel-serial converting plural serial-parallel converted packet signals outputted from output ports corresponding to the output lines of the plural subswitches. CONSTITUTION:Input lines (102-104) are converted to (PXQ) bits in parallel at a serial-parallel converters(P/S) (105-107). Here, P and Q show integers >=1. In other words, the plural subswitches to switch each of the plural bits of the serial-parallel converted packet signal are operated in parallel, and the parallel- serial conversion of the plural serial-parallel converted packet signals outputted from the output ports corresponding to the output lines of the plural subswitches are performed at each of the output lines. In such a way, it is possible to respond to the making of the line into high speed and the increment of the number of lines.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a groove forming technology for an ultra-high-speed packet switch.

(Prior art) A paper on conventional ultra-high-speed switches was presented at the 1984 International Switching Symposium (Int.
ernational Switching Synp.
osium 1984) knee, )-7th (A, T
``Asyncronous-Time-Day Vision, Technique'' presented by Homas et al.
s Time Division Technique
) J (Reference 1) is famous. There is also a paper published by Suzuki et al. at the 1988 IEICE Switching Study Group 5SE88-60 [Study of ATM Switch Architecture] (Reference 2).

In these papers, packet signals from multiple incoming lines are time-division multiplexed and written into memory for exchange operations. An example is shown in FIG.

This switch handles packets 501 to 50 input from the incoming line.
3 to serial-parallel (serial-parallel) converter (S/P) 5
Reduce speed at 09-511. After that, time-sharing bus 50
0 to perform time division multiplexing. Here, let V be the speed of entry.

When expanded into kbits by serial-parallel converters 509 to 511, the speed becomes ÷. However, if these N incoming lines are time-division multiplexed, an operating speed of ÷×N is required. Now, a packet has physical address information indicating which outgoing line it should be output to. As shown in FIG. 6(a), the header 600 is treated as the header 601 of the packet 600, and as shown in FIG. 6(b), it is treated separately from the packet 602.
In some cases, processing is performed in parallel as in 03. (However, the physical address here is used only for controlling the switch, and is not the logical address of the packet header.) Now, each time-division multiplexed packet is sent to the bus 500.
This will be broadcast to all the XL sides. Address filter (AF
) 512 to 514 are the above addresses (601
or 603), and if the packet should be output, it is received. Otherwise, the packet will not be received. In this way, reception is performed on the outgoing line written in the address. Thereafter, the data is written into buffer memories (FIFOs) 515 to 517 in a first-in, first-out manner. This FI
Outgoing line 504 by reading the packet from the FO memory.
~506.

(Problems to be Solved by the Invention) Since conventional packet switches perform time division multiplexing, as the line speed V and the number of lines N increase, the operating speed of the time division multiplexing unit also increases. Since the operating speed of the circuit is limited, it is necessary to increase the number of parallel bits k to suppress the increase in operating speed.

On the other hand, with the current LSI technology, it is difficult to integrate all of the elements shown in FIG. 5 into the same LSI because as N increases, the amount of memory and the number of gates increase. Therefore, blocks are divided as shown by broken lines in FIG. 5 to reduce the amount of memory and the number of gates, and to implement an LSI.

In such a case, the above-mentioned bit bus crosses between LSIs, causing a bin neck in the LSI.

For example, if V=160M and N=32, the LSI is 10
In order to keep the upper limit of operating speed to 40Mbps =
It becomes 128. In this way, many bi
It is difficult to operate a t bus at high speed. Therefore, k cannot be easily increased, and I101 of LSI
00 rise will be a bottleneck. That is, there is a problem in that it is difficult to increase the line speed or increase the number of lines.

The present invention solves the problems of the prior art and provides a method of configuring a switch that can sufficiently accommodate ultra-high speed lines and increase the number of lines.

(Means for Solving the Problems) In order to solve the above-mentioned problems in the present invention, in the first invention,
At each input line, the packet signal is serial-parallel converted and divided into multiple bits, and at least one of the serial-parallel converted bits is sent to the large port of the subswitch corresponding to the input line. The subswitch time-division multiplexes the plurality of packet signals input from the plurality of input ports, and transmits the time-division multiplexed packet signals to the plurality of output ports based on the address information of the packet. operating a plurality of sub-switches in parallel to exchange each of the plurality of bit numbers of the serial-parallel converted packet signal;
In each outgoing line, a high-speed packet switch is constructed by converting a plurality of serially-parallel converted packet signals outputted from the output ports of the plurality of sub-switches corresponding to the outgoing line into parallel-to-serial.

Furthermore, in the second invention, the packet signal is serial-parallel converted into a plurality of bits in each input line, and at least one bit of the packet signal among the plurality of serial-parallel converted bits is transmitted to the sub-switch. input to the input port corresponding to the input line, input a plurality of pieces of address information corresponding to packet signals from the plurality of input lines to the switch control unit,
The switch control unit determines to which outgoing line each packet signal is to be output based on the input address information, notifies the sub-switch of the identification information of the outgoing line for each packet signal, and outputs the outgoing line to the sub-switch. The switch time-division multiplexes the plurality of packet signals input from the plurality of human ports, and transmits the time-division multiplexed packet signals to output signals of the packets notified by the switch control unit. Based on line identification information, the sub-switch is outputted to one of the plurality of output ports of the sub-switch, and the plurality of sub-switches are operated in parallel to exchange each of the plurality of bit numbers of the serial-parallel converted packet signal. , for each outgoing line, a high-speed packet switch is configured by converting a plurality of serially parallelized packet signals outputted from the outgoing port corresponding to the outgoing line of the plurality of sub-switches into parallel to serial. .

Furthermore, in the third aspect of the invention, the packet signal is serially-parallel converted into a plurality of bits in each input line, and at least one bit of the packet signal among the plurality of bits subjected to the serial-parallel conversion is sent to the sub-switch. A plurality of pieces of address information corresponding to the packet signals from the plurality of input lines are input to the large port corresponding to the input line, and the switch control unit inputs each packet from the input address information. Determine which outgoing line to output to, find the write/read address of the packet buffer memory that stores each packet signal input to the subswitch, and set the write/read address of the packet buffer memory for each packet signal. Notify the information to the subswitch,
The sub-switch time-division multiplexes the plurality of packet signals inputted from the plurality of large ports, and performs time-division multiplexing on the basis of the write/read address information of the packet buffer memory notified from the switch control section. By writing and reading the multiplexed packet signal into the buffer memory, the multiplexed packet signal is output to one of a plurality of output ports, and each signal of a plurality of bits of the serial-parallel converted packet signal is exchanged. A plurality of sub-switches are operated in parallel, and for each output line, a packet signal divided into a plurality of bits output from an output port corresponding to the output line of the plurality of sub-switches is converted into parallel to serial. By doing this, a high-speed packet switch is constructed.

Furthermore, in the invention set forth in item 4, each incoming packet signal is broadcast simultaneously to a plurality of subswitches, and the subswitches only output circuits corresponding to M outgoing lines (MAN) out of N outgoing lines. and time-division multiplexing a plurality of packet signals input from the plurality of large ports, and outputting the time-division multiplexed packet signal to one of M outgoing lines based on address information of the packet. Configure a high-speed packet switch.

(Function) In the present invention, the time division multiplexing section, which is required to operate at the highest speed, is
It is configured to be closed inside the SI. This makes it possible to extend the degree of parallel expansion k of the time division multiplexing unit to the packet length, and since the internal speed can be faster than the Ilo of the LSI, it is easy to increase the speed of the time division multiplexing unit. Become. However, as mentioned above, the problem is that in order to integrate circuits for N lines into one LSI, the number of gates and amount of memory that must be accommodated in one LSI will increase significantly. . The present invention (1) divides the switch into bit slice type sub-switches (first to third inventions). Alternatively, ■ Since gates and memory are concentrated in the output side circuit, the number of gates and the amount of memory that can go into one sub-switch can be divided into sub-switches with a reduced number of outgoing lines (fourth invention). has been achieved to reduce

The first invention is a time division multiplex switch divided into bit slices. The P parallel subswitches operate in parallel, and each subswitch switches only the expanded bits when a packet is expanded into parallel bits. In this way, the number of gates and memories for N ports becomes ten, and one sub-switch can be placed inside the LSI, and since the time-sharing bus is also placed inside the LSI, it does not become a pin neck.

The second invention also has a similar bit slice type configuration, but furthermore, the control unit processes the packet address information all at once.
Only the processing results are notified to each sub-switch operating in parallel. In the first invention, the same address processing circuit is required for each sub-switch, but in the second invention, only one address processing circuit is required. Therefore, the number of gates is reduced.

The third invention further adds to the second invention by centralizing the write and read address control of the memory for storing packets in the control unit, and only the multiplexer and memory (RAM) are used as sub-switches. Similarly, the number of gates will decrease.

The fourth invention is to reduce the number of outgoing lines that one subswitch has and divide it. In other words, this focuses on the fact that gates and memory are concentrated in the output section. Each sub-switch has a time division multiplexer having all input lines, but only M (M<N) output lines which are smaller than the total number N of output lines. For example, a 32×32 switch is configured with eight 32×4 sub-switches. This sub switch is 1
Since it is implemented in one LSI, the speed of the time division multiplexing section can be easily increased as in the first invention.

(Example) A detailed explanation will be given below using the drawings. FIG. 1 is a block diagram showing an embodiment of the first invention. 100 and 101 are sub-switches. Incoming lines 102-104 are converted into PXQ bit parallel by serial-parallel converters (S/P) 105-107. Here, P and Q are integers of 1 or more. Here, it is assumed that the Q bits are input to each sub-switch. Therefore, the sub-switch is on the P side. One sub-switch has a structure similar to the conventional switch shown in FIG. That is, a time division multiplexing section consisting of serial parallel converters 108 to 110 and a time division multiplex bus 111, and address filters 113 to 115.
The operations within these sub-switches, which are also comprised of FiFo memories 116-118, are similar to those described with reference to FIG. However, care must be taken when handling packet addresses within the switch. The address of the packet outside the switch is as shown in (a) or b) in FIG.

In the case of serial arrangement as shown in FIG. 6(a), only the address section 601 is removed. Serial-parallel expansion targets only the 600 packet portion. In the case of FIG. 6(b), 603 is removed and only the packet portion of 602 is expanded into serial and parallel format. Now, address extraction is performed by serial-parallel converters 105-107. Addresses are sent to each sub-switch via address signal lines 124-126 in parallel with packet signal lines 127-129. Packets and addresses are multiplexed once, but the address filter (AF) 113~
At step 115, only the address part is inspected. packet is F
Once stored in the iFo memories 116-118, the packets are output and returned to the original packets by parallel-serial converters 119-121. Now, the operating speed of the switch in this case is as follows. Let the line speed be V and the number of lines N.

At the input to the subswitch, the packet is expanded into PXQbits, so the I10 speed is V. = and so on. Since the time division bus is N multiplexed, a throughput of ml glaze×N is required.

Therefore, 108 to 110 serial/parallel converters are required.

For example, if V = 160Mbps N = 32 p = s Q = l k = 32 then vi
10=v, n=20 Mbps Even if N or ■ is doubled, the increase in operating speed can be avoided by simply setting Q=2 or P=16.

The number of gates is as follows. In FIG. 5, the number of circuit gates for one line (including memory) is assumed to be G. In FIG. 5, each block (dashed line) has only G gates. In FIG. 1, it can be seen that for each sub-switch, if P is increased, the amount of gates required for each sub-switch can be reduced.

Next, an embodiment of the second invention is shown in FIG. The difference from FIG. 1 is that the packet address is processed by the control unit 238, and the write enable of the FiFos 217-219 is notified to the sub-switches 220-221 via signal lines 235-237.

This is the same address filter (AF) 113 in Figure 1.
All sub-switches must have this, but only the control unit has them. This allows sub switch 2
Since the number of gates 20 to 221 is further reduced and sub-switches operating in parallel can be centrally controlled, control management becomes easier. The address information of the packets input from the large greens 200-202 is separated from the packets by serial-parallel converters 203-205 and input to the control unit 238 by 206-208. The packet is expanded into PXQbits as in FIG. 1 and input into each subswitch 220 to 221 in Qbits. The control unit 238 sets the addresses 228 to 230.
serial-parallel (S/P) converter and time-sharing bus 23
1 for time division multiplexing. This operation runs in parallel with the S/P converters 212-214 of the subswitches 220.221 and the time division multiplexing of each packet on the time division bus 215.216. The address filters 232 to 234 check the address and determine which output port's FiFo 217 to 21
9 determines whether the packet should be stored. The result is 23
5 to 237, each FiFo217 to 21 of each sub switch
9 as a write enable signal. Based on this signal, the subswitch transfers the packet to the desired port's Fi.
Written to Fo. The packets are read from the FiFo and sent to parallel-serial (P/S) converters 222-224.
It is returned to its original form and output to outgoing lines 225-227.

In the case of such a configuration, in addition to the effects of the first invention, (2) AF on the sub-switch surface is unnecessary, and the number of gates is reduced.

■Since sub-switches operating in parallel can be centrally controlled, synchronization between sub-switches can be disrupted and management becomes easier.

There is an advantage.

Next, an embodiment of the third invention will be described using FIG. 3.

Basically, the difference from the embodiment of the second invention (Fig. 2) is F.
This is a method of controlling iFo memory. In FIG. 2, the FiFos of the same output port of each subswitch are all controlled by the same write/read address. Therefore, if this control circuit is concentrated instead of being provided in each sub-switch, the number of gates of the sub-switch can be further reduced. The subswitch only needs to have RAM. On the other hand, by doing so, the management of the synchronous operations of the sub-switches operating in parallel can be completely centralized, thereby further increasing reliability. Multiple processing of inputs from input lines 300 to 302 to bucket 1 is exactly the same as in FIG. 303-305 are serial-parallel converters, which separate addresses into 306-308 and input them to the control unit 343. Packets 309-311 are sent to sub-switch 320.
321. 312-314.328-330
Serial to parallel converter and time division bus 315.316
．． Time division multiplexing operation is performed by 331. Address of time division multiplexed packet is address filter (AF)
The AF of the port to be detected and received by 332 to 333 notifies the RAM controllers 354 to 356 of write enable. RAM controller is RAM317-319
This is to manage the FiFo.

In steps 337 to 339, each RAM of each subswitch is notified of the write address.

As a result, the time-division multiplexed packets are stored in the RAM of the desired port. The RAM controllers 354 to 356 of the control unit 343 output read addresses of the RAMs 317 to 319, thereby outputting packets. The packets output from the parallel-serial converters 322-324 are returned to their original form and output to outgoing lines 325-327.

In the embodiments of the first to third inventions, an output buffer type switch in which a memory is provided separately for each output line (refer to document ①) was shown, but a shared buffer type switch in which the memory b is shared by multiple output lines is shown. (Refer to Document ■). Even in that case, the present invention remains effective.

Next, an embodiment of the fourth invention will be described using FIG. 4.

In the fourth invention, the sub-switch is configured with a reduced number of outgoing lines, and incoming lines are connected by broadcasting them. For example, make eight 32x4 sub-switches for a 32x32 switch. In this figure, 4×
4 switches are made up of two 4x2 sub-switches. This is to reduce the number of sub-switch gates by paying attention to the fact that more than half of the gates of the switch are concentrated in the address filter and FiFo memory on the output side, and dividing them by output line. Since all the time division buses are included in the sub-switch, it has the effect of easily dealing with increases in line speed and number of lines, similar to the first to third inventions. Incoming lines 400 to 403 are broadcast and input to two sub-switches 408 and 409. Each sub-switch 408, 409 is similar to the switch in FIG.
417 and a time division bus 418.
It has a time division multiplexing section consisting of 419 parts. Also, address filters 420 to 423 and FiFo 424 to 42 for each port.
7 is divided into each sub-switch to lean on.

The present invention may be combined with the first invention, second invention, and third invention to form an NXM (M<N) subswitch into a Bit slice type. Alternatively, the control section may be separated. Furthermore, only the control section may have an NxM (M<N) configuration. FiFo memories for a plurality of outgoing lines of one subswitch may be configured as a shared memory. In either case, the present invention has its effects.

(Effects) According to the first to fourth aspects of the present invention, since a time-sharing bus with strict speed restrictions can be placed inside an LSI, it is possible to easily increase the speed of the time-sharing bus. Easily accommodates increases in numbers. According to the first to third inventions, by bit slicing the subswitch, even if the time division multiplexing section is placed inside the LSI, the LSI
It is possible to prevent an increase in the number of gates per hit. By centralizing the control section as in the second and third inventions, it is possible to further reduce the gate amount of the sub-switches, and the sub-switches operating in parallel can be centrally controlled and easier to manage. Further, according to the fourth invention, the number of output side circuits having a large number of gates can be reduced within the sub-switch. As described above, since the time division multiplexing section can be confined in an LSI and the LSI can be configured with an appropriate number of gates, future advances in LSI technology will make it possible to obtain even more economical, high-speed, and large-capacity packet switches.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a packet switch according to an embodiment of the invention set forth in claim 1. FIG. 2 is a block diagram of a packet switch according to an embodiment of the invention as claimed in claim 2. FIG. 3 is a block diagram of a packet switch according to an embodiment of the invention set forth in claim 3. FIG. 4 is a block diagram of a packet switch according to an embodiment of the invention set forth in claim 4. FIG. 5 is a block diagram of a conventional packet switch. FIG. 6 is a diagram showing how packets and their address information are transferred. In the figure 105-110.203-205.212-214.2
28~230.303~305°312~314.32
8~330.410~417...Serial parallel converter, 113~115.232~234.332~334.4
20~423...Address filter, 116~118.217~219.424~427...
・First-in-first-out (FIFO) memory, 119~121.222~224.322~324・
...Parallel serial converter, 354-356...RAM controller, 317-3
19...RAM0

Claims (4)

[Claims] (1) A packet switch that outputs packet signals from multiple input lines to one of multiple output lines based on the address information of the packet, and converts the packet signals from serial to parallel on each input line and divides them into multiple bits. The packet signal of at least one bit among the plurality of serial-parallel converted bits is input to the input port corresponding to the input line of the subswitch, and the subswitch The packet signal is time-division multiplexed, and the time-division multiplexed packet signal is exchanged and outputted to one of a plurality of output ports based on the address information of the packet, and the serial-parallel converted packet is A plurality of sub-switches that exchange each of a plurality of bit numbers of a signal are operated in parallel, and for each output line, a plurality of serial signals are outputted from an output port corresponding to the output line of the plurality of sub-switches. A packet switch that converts parallel-converted packet signals into parallel-to-serial. (2) A packet switch that outputs packet signals from multiple input lines to one of multiple output lines based on the address information of the packet, and converts the packet signals from serial to parallel on each input line and divides them into multiple bits. The packet signal of at least one bit among the plurality of serial-parallel converted bits is input to the input port corresponding to the input line of the subswitch, and the plurality of address information respectively corresponding to the packet signals from the plurality of input lines are input. is input to the switch control unit, and the switch control unit determines to which outgoing line each packet signal should be output based on the input address information, and the identification information of the outgoing line is inputted to the above for each packet signal. The subswitch time-division multiplexes the plurality of packet signals input from the plurality of input ports, and transmits the time-division multiplexed packet signals to the subswitch notified from the switch control unit. The packet is output to one of the plurality of output ports of the subswitch based on the identification information of the output line to which the packet is to be output, and the plurality of bit numbers of the serial-parallel converted packet signal are exchanged. The sub-switches of the plurality of sub-switches are operated in parallel, and in each outgoing line, a plurality of serial-parallel converted packet signals outputted from the output port corresponding to the outgoing line of the plurality of sub-switches are
A packet switch that performs parallel to serial conversion. (3) A packet switch that outputs packet signals from multiple input lines to one of multiple output lines based on the address information of the packet, and converts the packet signals from serial to parallel on each input line and divides them into multiple bits. The packet signal of at least one bit among the plurality of serial-parallel converted bits is input to the input port corresponding to the input line of the subswitch, and the plurality of address information respectively corresponding to the packet signals from the plurality of input lines are input. is input to the switch control unit, and the switch control unit determines which outgoing line each packet should be output to based on the input address information, and a packet buffer that stores each packet signal input to the sub-switch. The write/read address of the memory is obtained, and the write/read address information of the packet buffer memory is notified to the subswitch for each packet signal, and the subswitch receives the plurality of packets input from the plurality of input ports. By time-division multiplexing the signals and writing/reading the time-division multiplexed packet signals to/from the buffer memory based on the write/read address information of the packet buffer memory notified from the switch control unit, A plurality of sub-switches are operated in parallel to output signals to one of a plurality of output ports, and each of the plurality of bits of the serial-parallel converted packet signal is exchanged, and in each output line, A packet switch characterized in that a plurality of serial-to-parallel converted packet signals outputted from output ports corresponding to the outgoing lines of the plurality of sub-switches are subjected to parallel-to-serial conversion. (4) A packet switch that outputs packet signals from multiple incoming lines to one of N outgoing lines based on the address information of the packet, and broadcasts each incoming packet signal to multiple subswitches, and the subswitch has only output circuits corresponding to M outgoing lines (M<N) out of N outgoing lines, and time-division multiplexes a plurality of packet signals input from the plurality of input ports, and A packet switch characterized in that the time-division multiplexed packet signal is outputted to one of M outgoing lines based on the address information of the packet.