JPH0267451U - - Google Patents

Info

Publication number
JPH0267451U
JPH0267451U JP12849989U JP12849989U JPH0267451U JP H0267451 U JPH0267451 U JP H0267451U JP 12849989 U JP12849989 U JP 12849989U JP 12849989 U JP12849989 U JP 12849989U JP H0267451 U JPH0267451 U JP H0267451U
Authority
JP
Japan
Prior art keywords
switch
input terminal
switches
mode
integrating means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12849989U
Other languages
English (en)
Other versions
JPH0337075Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989128499U priority Critical patent/JPH0337075Y2/ja
Publication of JPH0267451U publication Critical patent/JPH0267451U/ja
Application granted granted Critical
Publication of JPH0337075Y2 publication Critical patent/JPH0337075Y2/ja
Expired legal-status Critical Current

Links

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  • Measurement Of Resistance Or Impedance (AREA)

Description

【図面の簡単な説明】
第１図は本考案のサンプリング積分回路のブロ
ツク図。第２図は本考案のサンプリング積分回路
のタイミング図。 １：増幅器、２：位相検波器、３，４：演算増
幅器、５：制御回路、ＳＷ１〜ＳＷ４：スイツチ
。

Claims (1)

    【実用新案登録請求の範囲】
  1. 被測定信号の伝送路を接地するための第１スイ
    ツチと、前記伝送路と積分手段の第１入力端子と
    の間に接地された第２スイツチと、前記積分手段
    の出力部と前記積分手段の第２入力端子との間に
    設けられた第３スイツチと、前記積分手段の第２
    入力端子と接地間に設けられたコンデンサと、前
    記第１、第２、第３スイツチを制御する制御回路
    とから成り、前記制御回路は前記第１、第３スイ
    ツチを閉じてオフセツト補償するための第１モー
    ドおよび前記第１、第３スイツチを開いて前記被
    測定信号のサンプリング積分をおこなうための第
    ２モードを有し、前記第１、第２モードのいずれ
    のモードにおいても前記積分手段をリセツトする
    ことなく実質的には同一複数回数前記第２スイツ
    チをくり返し開閉してサンプリングすることを特
    徴とするサンプリング積分回路。
JP1989128499U 1989-11-02 1989-11-02 Expired JPH0337075Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989128499U JPH0337075Y2 (ja) 1989-11-02 1989-11-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989128499U JPH0337075Y2 (ja) 1989-11-02 1989-11-02

Publications (2)

Publication Number Publication Date
JPH0267451U true JPH0267451U (ja) 1990-05-22
JPH0337075Y2 JPH0337075Y2 (ja) 1991-08-06

Family

ID=31381894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989128499U Expired JPH0337075Y2 (ja) 1989-11-02 1989-11-02

Country Status (1)

Country Link
JP (1) JPH0337075Y2 (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595180A (en) * 1979-01-10 1980-07-19 Toshiba Corp Error correcting unit of integrator
JPS5779580A (en) * 1980-09-08 1982-05-18 American Micro Syst Off-set compensation for integrator with capacitor to be switched

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595180A (en) * 1979-01-10 1980-07-19 Toshiba Corp Error correcting unit of integrator
JPS5779580A (en) * 1980-09-08 1982-05-18 American Micro Syst Off-set compensation for integrator with capacitor to be switched

Also Published As

Publication number Publication date
JPH0337075Y2 (ja) 1991-08-06

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