JPH0267614A - System clock circuit for microcomputer - Google Patents

Abstract

PURPOSE:To prevent the generation of malfunction in a dynamic circuit in a slow mode and to reduce the cost of the title circuit by outputting an active output signal for a fixed time without proportionating a prescribed system clock in system clocks to an oscillation clock. CONSTITUTION:An AND circuit 3 inputs an output and an ordinary system clock phi1 through an inverter 2 for a delay circuit 1 for inputting the clock phi1 as an internal clock and outputs its AND operation result to a multiplexer 4. The multiplexer 4 selects one output signal from plural input signals in accordance with a mode signal CLM and outputs a new system clock phi1*. The duty of the clock phi1* is activated only for the fixed time without being proportionated to the oscillation clock. Thereby, the level drop of an output VO in a slow operation mode can be neglected, the generation of malfunction can be prevented, the cost can be reduced without extending the gate length of a transistor and the lower limit of the frequency of system clocks to be used can be expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and particularly to a system clock circuit.

[Conventional technology]

In order to explain a conventional example of a system clock circuit, a dynamic circuit as shown in FIG. 4 will be explained as an example.

A P-channel transistor TP (hereinafter referred to as TP) has a source connected to a power supply, a drain connected to an output VO, and a sampling clock φS (hereinafter referred to as φS) inputted to a gate signal. Furthermore, an N-channel transistor T is connected to VO.
The drain of NI (hereinafter referred to as TN1) is connected, and TNI
The input signal INI is input to the gate signal of , and the source is connected to the drain of the N-channel transistor TN2. Below, N-channel transistors TN2 to TNn (
(hereinafter referred to as TN2 to TNn) are similarly connected in a vertically stacked configuration, and the input signal IN2 is connected to each gate input.
~INn is input. N channel transistor T
The source of Nn is connected to the drain of an N-channel transistor TN (hereinafter referred to as TN), the source of TN is connected to GND (ground), and a gate signal φS is input. φS is a clock signal in phase with the system clock φ1 (hereinafter referred to as φ1). φ1 will be explained next.

The operation of the dynamic circuit shown in FIG. 4 will be explained using the timing diagrams shown in FIGS. 5(a) and 5(b).

In FIGS. 5(a) and (b), φ1 is a clock signal created by frequency-dividing an oscillation clock (hereinafter referred to as oscillation clock) with an oscillation frequency f that is input to the microcomputer, and is the mode of the system clock. This is a clock that outputs output signals with different frequency division ratios under the control of a mode signal CLM (hereinafter referred to as CLM) that controls switching. In this example, a two-phase clock mainly using φ1 is used as the system clock. Further, the operation mode in which a clock with a small frequency division ratio is selected by the mode signal CLM is called a high-speed operation mode, and the operation mode in which a clock with a large frequency division ratio is selected is called a low-speed operation mode. As described above, in the high-speed operation mode and the low-speed operation mode, φ1 is created by frequency-dividing the oscillation clock, so the period of φ1 is proportional to the oscillation frequency.

The operation in the high-speed operation mode will be explained using the timing diagram in FIG.
Since ~INn becomes a high level (hereinafter referred to as H), the N-channel transistors TN1 to TNn also become conductive, and only TN becomes non-conductive. Therefore, TNI~
Source, drain and capacitor of each transistor of TNn
c1 is charged with ``10 degrees'' charge. Next, φS is “
During the "H" period, TP is non-conductive and TN is conductive.If TNI is selected during this period, the input signal INI is "L" and the input signals IN2 to INn are "L".
1 HII, TN2 to TNn also become conductive, and the charges precharged in the sources and drains of TN2 to TNn and the train of TN are discharged.

- Since the power signal INI is ``L'', TNI is in a non-conducting state and the output signal 0 is set to ``H'' level.As a weak leakage current flows through TNI, the capacitor c1 is precharged. As the electric charge decreases over time, the level of the output VO also decreases, which is why φS
Since the active output time is short and the amount of electricity is small, the drop in the level of the output VO is negligible.

Next, the operation in the low-speed operation mode will be explained using the timing diagram of FIG. 5(b). First, during the period when φS is "L", "10" charges are charged to the source, drain, and capacitor C1 of each of the transistors TNI to TNn, similarly to the high-speed operation mode.

Next, during the period when φS is "H11", T
If NI is selected, TNI becomes non-conductive and the output signal VO is held at the "H" level. However, T.N.
Since a weak leakage current flows from I, the capacitance C1
Since the precharged charge decreases with time,
The level of the output VO also decreases with time. Therefore φ
In the low-speed operation mode in which the active output time of S is long, the level of the output VO decreases significantly and disappears at the H'' level, resulting in malfunction.

[Problem to be solved by the invention]

As mentioned above, in a microcomputer with conventional system clock speed switching, the time between active output and inactive output of the system clock is equal to the oscillation frequency f in the high-speed operation mode and the low-speed operation mode.
The length was proportional to Therefore, in order to prevent malfunctions in dynamic operation circuits such as decoders in low-speed operation modes, it is necessary to reduce leakage, and for this purpose, the gate length of the transistor in the dynamic operation circuit is increased, which increases the chip area and increases cost. There are drawbacks. Another drawback is that it is not possible to set a wide lower limit on the frequency of the system clock that can be used.

[Means to solve the problem]

A system clock circuit for a microcomputer according to the present invention includes a circuit that inputs an internal clock generated by an oscillation clock input to the circuit and outputs an active output signal for a certain period of time;
A multiplexer selects the output signal and the internal clock using a mode signal and outputs a system clock signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an example of the configuration of a system clock circuit according to an embodiment of the present invention. φ1, which was used as the system clock in the conventional example, is input to the delay circuit 1 as an internal clock.
Its output is connected to inverter 2. The output of the inverter 2 and φ1 are input to the 2AND circuit 3, and its output becomes the input of the multiplexer 4. The multiplexer 4 is a circuit that selects one output signal from a plurality of input signals according to the mode signal.
φ1 is inputted to , and the mode signal CLM is also connected to it, and its output becomes the system clock φ1* (hereinafter referred to as φ1*) of the present invention as φ1*. (As an example, we will discuss a two-phase clock and assume that the present invention is used for φ1.) Next, an example of the system clock of the present invention will be explained using FIG. 2. This is a circuit in which the multiplexer 4 of the circuit of the present invention shown in FIG. 1 is configured as a gate, and the dynamic circuit shown in FIG. 4 is connected.φ
φ1* is connected to S.

Furthermore, the mode signal CLM is applied to the input of the composite gate 6. Composite gate 6 is 2AND2AND2OR'? φ1 is inputted to the remaining input of the 2AND which is configured as "2AND" and receives the mode signal CLM.Furthermore, the output of 2AND3 and the output of the inverter 5 are inputted to the remaining 2AND of the composite gate 6. 5 is the mode signal CL
M is input.

The operation of the embodiment shown in FIG. 2 in the high-speed operation mode will be described using the timing diagram of FIG. 3(a). In the high-speed operation mode, in the composite gate 6, the mode signal CLM activates the 2AND of the composite gate 6 to which φ1 is input, and Φ1 is selected, so that the output is in phase with φ1. Therefore, the operation is the same as that described in the conventional high-speed operation mode.

Next, the operation in the low-speed operation mode will be explained using the timing diagram of FIG. 3(b). In slow operating mode,
The composite gate 6 is connected to the 2AND circuit 3 by the mode signal CLM.
The output of the 2AND circuit 3 to which is input becomes active, and the output of the 2AND circuit 3 is selected. Also, 2A
Since the output of the inverter 2 and φ1 are input to the ND circuit 3, it becomes "H" for a certain period of time from the rising edge of φ1.Therefore, the duty of φ1* is not proportional to the oscillation clock and is active only for a certain period of time ( ” becomes “H” level). Therefore, during the period when φS is “L”, as in the conventional low-speed operation mode, the source, drain, and capacitor C1 of each transistor TN1 to TNn are charged with “+” charges.Next, when φS is “H” During this period, as in the conventional low-speed operation mode, TNI becomes non-conductive and the output signal VO is held at the H" level. However, since a weak leakage current flows from TNl, the charge precharged in C1 is decreases with time, the output ■
The level of 0 is also decreasing. However, if the delay time of the delay circuit 1 is set to such an extent that the decrease in charge can be ignored, φ1* will be active (at "H" level) only for a certain period of time, so that the decrease in the level of VO can be ignored and malfunction will not occur.

Although the embodiment has been described with respect to the tarlock φ1, similar effects can be obtained by using the number of clock phases (for example, a two-phase clock) or other system clocks.

〔Effect of the invention〕

As described above, the present invention allows a predetermined system clock among the system clocks to output an active output signal for a fixed period of time without being proportional to the oscillation clock in a system clock circuit of a microcomputer. This has the effect of preventing malfunctions of the dynamic circuit in low-speed mode, reducing costs by eliminating the need to increase the gate length of the transistor, and widening the lower limit of usable system clock frequencies.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 (a) is an operation timing diagram of the high speed mode of the present invention, and Fig. 3 (b) is a block diagram of the present invention. Figure 4 is an example of a dynamic circuit according to the conventional technology; Figure 5 (a) is an operation timing diagram in the conventional high speed mode; Figure 5 (b) is the conventional low speed mode. FIG. 1...Delay circuit, 2...Inverter, 3...2A
ND circuit, 4... Multiplexer, 5... Inverter, 6... Composite gate, TP... P channel transistor, TN - TN 1 to TNn... N channel transistor, CLM... Mode signal, φS...Sampling clock, INI~INn...Input signal, ■
0...Output signal, C1...Capacity.

Claims (1)

[Claims] A system clock circuit of a microcomputer includes a circuit that inputs an internal clock generated by an oscillation clock input to the circuit and outputs an active output signal for a certain period of time, and a circuit that outputs an active output signal for a certain period of time, and a circuit that outputs an active output signal for a certain period of time, and a circuit that outputs an active output signal for a certain period of time. A system clock circuit for a microcomputer, comprising a multiplexer for selecting and outputting a system clock signal.