JPH0267632A - Branch instruction construction method in electronic computers - Google Patents

Abstract

PURPOSE:To prevent the reduction of subroutine utilization effect and deterioration of performance by forming a field specifying a register for storing the succeeding instruction address to be executed at the time of failure of a branch condition. CONSTITUTION:Bits 8, 9 (R1) are a field for specifying a register to a condition branch instruction(BC). When a condition branch instruction BCAL capable of storing link information specifying R1 = 2 is executed, the succeeding instruction address of the BCAL is stored in a register BRA and branched to an address specified by the 2nd operand B2/D2. When the processing of the branch is to be executed as a subroutine, the final instruction of the subroutine is a BC for obtaining a return function and the T1 part of the BC specifies unconditional branch. When the B2 part of the BC specifies the BRA and the D2 part is '0', the address saved to the BRA by the BCAL addresses a control memory as the succeeding instruction address, so that operation can be returned from a subroutine to a main routine.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for configuring branch instructions in an electronic computer, and more particularly to a method for configuring a conditional branch instruction suitable for a microprogram, etc. included in a channel device of an electronic computer. .

[Conventional technology]

Branch instructions in conventional electronic computers include conditional branch instructions (BC) that determine whether or not to take a branch, and link information (next instruction address: add own instruction length to own instruction address) while branching. A branch instruction that can store link information (B A
It is broadly divided into L). Regarding this type of branch instruction, see, for example, the HITACM series processing unit manual (
Manual number: 8080-2-001) 197-19
8 and pages 200-201.

[Problem to be solved by the invention]

The channel device of an electronic computer is generally equipped with a microprogram and performs input/output control independently of the central processing unit, but the frequency of use of branch instructions in the microprogram of this channel device is 30 to 40%, of which BC and BAL is about 90%, and the frequency of unconditional branches is small.Especially in channel devices, microprograms are required to be stored in a limited control storage capacity to prevent increases in manufacturing costs. , microprograms make extensive use of subroutines to achieve required functions within a limited capacity.

Furthermore, in the microprogram of the channel device,
BC is frequently used for testing the contents of the channel command word (CCW), testing the device status byte (DSB) sent by input/output devices, testing the internal status of subchannels and channel devices, etc. The branch destination when the condition of BC is satisfied is set as a subroutine, and the branch from the subroutine to the above B
Returning to the next address of C satisfies the storage of the microprogram in the limited control storage capacity due to the extensive use of subroutines described above. As an example, upon returning from a subroutine CCW read process,
The read CCW contents jump within the channel T I
When testing whether or not C) is true using BC, the condition is established, so the operation of branching back to the subroutine CCW request processing can be cited.

When such processing is realized using conventional BC and BAL, there is a BAL at the branch destination of BC, a branch is made to a subroutine by this BAL, and the return destination from the subroutine is the BC that exists next to the BAL, Since the branch destination of this BC is programmed to be the next address of the BC, the BC cannot directly save link information.

That is, in order to set the branch destination when the BC condition is satisfied as a subroutine and return from the subroutine, two steps of branching must be repeated. For this reason, two additional branch instructions are required to utilize the subroutine to route the microprogram to the limited control storage capacity, which cancels out the effect of using the subroutine and also reduces performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a new conditional branch instruction capable of storing link information in order to solve the above-mentioned problems, and to prevent a decrease in effectiveness and performance when using subroutines.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a conditional branch instruction (B C
) is provided with a field that specifies a register that stores the address of the next instruction to be executed when the branch condition is not satisfied.

[For production]

A new conditional branch instruction in which a field specifying a register to store the next instruction address is added to the first operand, which is the condition field of the conventional BC, will be referred to as BCAL (conditional branch instruction capable of storing link information).

When BCAL is executed, the next instruction address of BCAL is saved to the designated register.

Further, when the condition specified in the condition field of the BCAL is satisfied, the process branches to the address indicated by the second operand of the BCAL. If the process executed from this branch destination is made into a subroutine, the final instruction of this sub-tine is a BG with an unconditional branch specified in the condition field, and the BCAL is linked in the second operand of the BC. By specifying the register storing the information, it is possible to immediately return from the subroutine to the next instruction of the BCAL.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

The target is the microprogram of the channel device,
Assume that all the microinstructions are 32 bits long. It is also assumed that the control storage capacity of the channel device is 8 words.

(a) in FIG. 1 is the format of a normal conditional branch instruction (BC:), and bits 0 to 7 are operation codes (op) for identifying BC.

Bits 10-15 are the condition field of the first operand (
Bits 16 to 29 are the second operand that specifies the branch destination address;
(B,) specifies the base register number, bit 20
~29 specifies the displacement (B2) from the value of the base register specified by B2. Note that in a normal conditional branch instruction, bits 8 to 9 and bits 30 to 31 are ignored.

FIG. 1(b) shows the format of a conditional branch instruction (BCAL) that can store link information newly introduced by the present invention, and the pins 1-0 to 7 are used to identify BCAL. Operation Kodo (OII), Pi 1~8~
9 (RL) is a field that specifies the link information storage register newly added to BC, and bit 1
Condition field (T) from 0 to 15 and bits 16 to 29
The second operand (B2/D2), bits 30 to 31 are the same as BC in FIG. 1(a).

In this embodiment, since the control memory capacity of the channel is two words, the base register (BR) consists of a total of 13 bits, bits 01 to 15, as shown in FIG. Addressing Memory 6Also, as shown in Figure 2, the microprogram can specify base registers up to BRO-8, but BRO-7 do not actually exist as registers; D
2 par 1- becomes the address of direct control storage. B R8
~B has substance as a register, and each corresponds to 0 to 3 of R1 of BCAL, and when BCAL is executed, the next instruction address is stored in one of registers B R8 to B according to the value of R1 as link information. is stored as .

For example, when a B CA L specifying R1=2 is executed, the next instruction address of the BCAL is stored in the register BRA, and a branch is made to the address specified by the second operand B2/D2. When processing at a branch is made into a subroutine, the final instruction of the subroutine is a BC for realizing a so-called return function, and the T of the BC is
The 4th part specifies an unconditional branch. By specifying BRA for the B2 part of the BC and setting the B2 part to 0,
Since the address saved to BRA at BCAL addresses the control memory as the next instruction address, it is possible to return from the subroutine to the main routine.

The branch destination when the BC condition is met is made into a subroutine.

The flow from the subroutine to return is the same as the conventional B.
When realized using C and BAL, it becomes as shown in Fig. 3.

Here, instructions 300 to 302 are the main routine, and 301 of them is BC.

If that condition is met, a branch is made to instruction 310.

310 is BAL, and subroutines 320 to 32N
At the same time, the address of instruction 311 is saved to the pace register (BR). Final instruction 3 of subroutine
2N is an unconditional BC, and in its B2 part, the above B
Specify R and return to command 31. Furthermore, 311
is also an unconditional BC, and branches (returns) to instruction 302 of the main routine in its B2/D 2 part.

If the same process as that shown in FIG. 3 is realized using the new conditional branch instruction (BCAL) in which link information can be stored as shown in FIG. 1(b), the result will be as shown in FIG. 4. Here, the instruction 301 is BC in FIG. 3, but BCAL is used in FIG. 4. When instruction 301 (BCAL) is executed, its B2/B
The second part branches directly to the first instruction 320 of the subroutine, and the address of the instruction 302 is saved to the pace register (BR) specified in the R1 part. The final instruction 32N of the subroutine is an unconditional BC;
By specifying the BR in the second part and setting the B2 part to 0, when the instruction 32N is executed, it is possible to directly return to the next instruction 302 of the main routine.

〔Effect of the invention〕

As is clear from the above explanation, according to the branch instruction configuration method of the present invention, link information can be saved even though it is a conditional branch instruction, so that the total instructions of a program to realize a branch to a subroutine and a return from a subroutine can be saved. This has the effect of reducing the number of programs, improving processing performance, and facilitating program design.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the format of a normal conditional branch instruction and a conditional branch instruction that can store link information according to the present invention, and FIG. 2 is an example of a table for base register allocation according to the conditional branch instruction of the present invention. 3 is a flowchart when a conventional branch instruction is used, and FIG. 4 is a flowchart when a conditional branch instruction capable of storing link information of the present invention is used. 300-302...Main routine, 301...B
CAL command, 320-32N - Subroutine. Figure 1 C) Figure 2

Claims (1)

[Claims] (1) In a conditional branch instruction that includes a first operand that specifies a branch condition and a second operand that specifies a branch destination address when the branch condition is met, add a register that stores the address of the next instruction to be executed when the branch condition is not met. A method for configuring branch instructions in an electronic computer, characterized by providing a field for specifying them.