JPH0267747A - Bipolar cmos gate array circuit device - Google Patents

Abstract

PURPOSE:To produce a supply-to-supply capacity without incrseaing a number of processes and to prevent erroneous operation due to supply noise by using an N<+>type buried layer formed as a collector electrode, as one of supply interconnection layers to a basic cell matrix. CONSTITUTION:On a semiconductor substrate 100, there are provided an input/ output circuit 101 and a basic cell matrix consisting of basic cells 102. Further, metallic supply interconnection layers 103 extended vertically and metallic supply interconnection layers 105 extended transversely are provided reticulately while N<+>type buried layers 104 are provided between the basic cell matrix and the input/output circuit 101. Since N<+>type buried layers 111, 112 are formed as a collector electrode of a vertical NPN bipolar transistor or a substrate electrode of a P-type MOSFET, the N<+>type buried layers for interconnection with a power supply can be formed without increasing a number of processes. Parasitic PN junction capacity can be used effectively as a supply-to-supply capacity for absorbing supply noise.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bipolar CMOS gate array circuit device in which an N-type buried layer formed as a collector electrode is used as one power supply wiring layer to a basic cell matrix. This stabilizes the power supply potential and improves wiring efficiency.

[Conventional technology]

In the conventional bipolar CMOS gate array circuit device, as shown in Figure 3, metal wiring for power supply is arranged and routed in a mesh pattern from the input/output circuits arranged around the basic cell matrix to the basic cell matrix. .

[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, a metal wiring layer with a small capacitance between power supplies is used as a power supply wiring, and therefore the power supply potential fluctuates significantly due to the operation of the active element, which deteriorates the circuit characteristics. This has the problem of inducing deterioration of the Furthermore, in the prior art, a part of the metal wiring layer is used as a power supply wiring layer, so there is a problem in that the wiring efficiency of the signal wiring formed by the metal wiring layer is significantly reduced.

SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a bipolar CMOS gate array circuit device with stable circuit characteristics and high wiring efficiency.

[Means for Solving the Problems] The bipolar CMOS gate array circuit device of the present invention comprises: a) a bipolar CMO3 hybrid semiconductor integrated circuit device consisting of bipolar transistors and complementary MOSFETs, and b) a basic structure mainly consisting of complementary MOSFETs. With cell.

C) a basic cell matrix formed by arranging a plurality of the basic cells in a matrix; d) an input/output circuit mainly composed of bipolar transistors; e) a low resistivity N9 type buried layer; A type embedding layer is arranged between the basic cell matrix and the input/output circuit, and is one of the power supply wiring layers of the basic cell matrix.

〔Example〕

FIG. 1 shows a layout diagram of a bipolar CMOS gate array circuit device in an embodiment of the present invention.

As is clear from the figure, a basic cell matrix consisting of basic cells 102 and an input/output circuit 1 are provided on a semiconductor substrate 100.
01, a vertical metal power wiring layer 103 and a horizontal metal power wiring layer 105 are arranged in a mesh pattern on the basic cell matrix, and an N0 type buried layer 104 is placed between the basic cell matrix and the input/output circuit 101. By forming the bipolar CMOS gate array circuit device of the present invention, it is possible to easily form the bipolar CMOS gate array circuit device of the present invention.

FIG. 2 is a main cross-sectional view of the basic cell, and as is clear from the figure, the N-type buried layers 111 and 112 are formed as the collector electrode of a vertical NPN bipolar transistor or the substrate electrode of a P-type MOSFET. Therefore, an N-type buried layer for power supply wiring can be formed without increasing the number of steps.

Furthermore, since the N''' type buried layer 104 has the P- semiconductor substrate 100 biased to the other potential, the parasitic PN junction capacitance can be utilized as a power supply capacitance for absorbing power supply noise.

[Effect of the invention 1 As described above, according to the present invention, by using the N″″ type buried layer as one power supply wiring, the capacitance between the power supplies can be formed without increasing the number of steps, and the power supply noise caused by power supply noise can be formed. This has the effect of preventing circuit malfunctions.

Further, according to the present invention, since the metal power supply wiring layer can be replaced with an N-type buried layer, the signal wiring efficiency can be improved, that is, the chip cost can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of a bipolar CMOS gate array circuit device of the present invention. FIG. 2 is a sectional view of a basic cell in the bipolar CMOS gate array circuit device of the present invention. FIG. 3 is a layout diagram of a conventional bipolar CMOS gate array circuit device. 100, 110.130 P-semiconductor substrate 101.131... Input/output circuit 102.132... Basic cell 103.133... Vertical metal power supply wiring 104.1
11.112...N3 type buried layer 105.135...Horizontal metal power supply wiring 113...
...P+ type buried layer 114...Deep N3 diffusion layer 115.119...N type walled diffusion layer 116...
...N-type insertion layer 117...Base diffusion layer 118...Emitter diffusion layer 120.123...P4 diffusion layer 121.122...N+ diffusion layer 124. 125...Gate electrode 126......P-type enclosure type diffusion layer or above Applicant: Seiko Epson Co., Ltd. Agent Patent attorney Masaharu Kamiyanagi (and 1 other person) 1st Co. 2nd session

Claims (1)

[Claims] a) Bipolar transistor and complementary M@O@SFE
In a bipolar CM@O@S hybrid semiconductor integrated circuit device consisting of T, b) a basic cell mainly consisting of complementary M@O@SFETs, and c) a basic cell matrix consisting of a plurality of the basic cells arranged in a matrix. and d) an input/output circuit mainly composed of bipolar transistors, e) a low resistivity N^+ type buried layer, and f) the N^+ type buried layer.
A bipolar CM@ characterized in that a ＾+ type buried layer is arranged between the basic cell matrix and the input/output circuit, and also serves as one power supply wiring layer of the basic cell matrix.
O@S gate array circuit device.