JPH026774A - Lsi testing method - Google Patents

Abstract

PURPOSE:To prevent the increase of the number of test terminals of an LSI irrespective of the diversification of a test mode by bringing each output of the number of parallels of a shift register and a test enable signal to gate processing and outputting selectively test data. CONSTITUTION:On a testing circuit 1 provided with a prescribed number (m) of testing circuits 21-2m for parting to a prescribed number of logic circuits 11-(1m+1) for each separate function and inputting an input clock CK of a pre-stage circuit 11 as it is to a clock terminal of a post-stage circuit 12, a test signal generating part 3 consisting of a shift register 31 and a gate 32 is provided. The shift register 31 shifts inputs of test use data TDATA of each separate function by the number of stages (m) being equal to the number of inserting circuits (m) of the testing circuits 21-2m by a test use clock TCLK and outputs them in parallel. The gate 32 brings the parallel shift outputs of the shift register 31 to gate processing by a test enable signal TE which is inputted at the time of test, and supplies output signals To to Tm-1 to the testing circuits 21-2m.

Description

[Detailed Description of the Invention] [Summary] Regarding test terminals for testing provided in a large-scale integrated circuit LSi in which logic circuits with various functions are highly integrated in a multi-stage configuration, the integration of the LSi is progressing. The purpose is to allow only a fixed number of test terminals to be provided on T and Si even if the number of stages in a multi-stage logic circuit increases, the functions required for the logic circuit become complex, and test motes become more diverse. The circuit is divided into a certain number of circuits according to function, and a test circuit of a certain number m is installed at each divided point to input the input clock CK of the previous stage circuit directly to the clock terminal of the subsequent stage circuit during testing.
In a Si test circuit, the input of the test data T DATA of the test circuit is connected to the test I clock TCI, K
The number of stages equal to the number of inserted circuits in the test circuit is selected by gate processing and selecting a shift register which is shifted by n and outputs in parallel, and a constant number m of parallel outputs of the shift register by gate processing using the test enable signal TE input during testing. A test signal generating section is provided, and the output selected by the gate of the test signal generating section is supplied to a test circuit for testing.

[Industrial application field]

The present invention relates to the testing of large-scale integrated circuits LSi in which logic circuits with a multi-stage configuration and various functions are highly integrated, and in particular,
This invention relates to a test terminal provided in an i-circuit for testing.

[Conventional technology]

A circuit with deep logic that has a multi-stage configuration and various functions, such as a multi-stage counter, uses a large number of input clocks (or clocks as a reference) until the clock input to the input terminal changes the output signal output to the output terminal. Therefore, the number of test patterns required for the LSi test method, which tests highly integrated LSi circuits with deep logic, is enormous, which not only reduces test efficiency but also makes it more prone to mistakes. Become. Therefore, in order to avoid reducing the number of input clocks or patterns required for testing, the LSi testing method divides the 2r one-stage counter circuit into several parts (two in the figure), as shown in Figure 4. In between, a test circuit 21 is provided for receiving and passing the clock CK manually input to the clock terminal CK of the first counter CNT11 in the previous stage to the clock terminal CK of the second counter CNT12 in the subsequent stage during testing. LS is the test terminal that inputs the test signal TesL that drives 21.
Provided at i.

The counter's eggplant 1 circuit 21 is ant game 1.211.
Ann I Gate 212. Noah Gate 213. It is composed of an inverter 214, and during testing, the AND gate 211 and the NOR gate 213 of the eggplant 1-circuit 21 set the test terminal Te5t as code "1." (Tes i enable),
The signal with the sign "11"' inverted by the inverter 214 causes the clock terminal CK of the first counter CNT 11 to
The clock CK input to the second counter CNT is directly input to the second counter CNT.
12 clock terminal CK. During non-testing, the AND gate 212 and the NOR gate 213 of the test circuit 21 change the final stage output port of the first counter CNT 11 to the second counter in the normal mode with the symbol "■" of the test terminal Test. Clock terminal CK of CNT 12
The counter is passed to the counter, and functions as a 2n-stage counter.

The number of logic stages of the counters 11 and 12 of the multi-stage logic circuit integrated in the LSi circuit is further increased to 20, and the function required for the logic circuit is not a simple counter, but a logic that controls another counter with the output of one counter. As the circuit becomes more complex, the test modes become more diverse. Accordingly, as shown in Figure 4B, the number of stages M that divides a multi-stage logic circuit with various functions is increased, and tests are inserted at the divided locations. The number of test terminals (m) depends on the number of inserted circuits (m) of circuits 21 to 2m.
We are responding by increasing the number of

[Problem to be solved by the invention]

In the conventional technology, as mentioned above, the number of logic stages of a multi-stage logic circuit integrated in an LSi circuit increases, the functions required for the logic circuit become complex, and the test modes become diversified. The number of test circuits inserted into the test circuit 2 that divides the circuit and inputs the input clock of the previous circuit to the subsequent circuit [The number of test terminals m is increased according to n, but only a certain number of terminals are provided. Increasing the number of test terminals that are not normally used in an LSi circuit that does not have the same number of test terminals has the problem of limiting the number of terminals of the original functional circuit, resulting in cost savings and waste.

Even if the number of logic stages of a multi-stage logic circuit integrated in an LSi circuit increases, the functions required for the logic circuit become complex, and the test modes become more diverse, the number of test terminals provided on the LSi remains constant. The challenge is to make it possible to do so.

[Means to solve the problem]

As shown in FIG. 1, this problem involves dividing the above-mentioned logic circuit by dividing the input of the test data T DATA for each function of the LSi using the test clock T CLK, and dividing the input clock CK of the previous stage circuit 11. A shift register 31 that is shifted by the number m of stages equal to the number m of circuits of the test circuit 2 that is input to the subsequent stage circuit 12 as it is, each output of the parallel number m of the 2-shift register 31, and the test enable signal T [i and The LSi
As circuits become multistage, the required functions become more complex, and the test modes become more diverse, testing methods that require dividing and inserting circuits are becoming more difficult.
Even if the number m of circuits 2 increases, the test terminals provided on the LSi are the negative clock TCLK and negative 1.
This problem is solved by the configuration of the present invention in which it is sufficient to prepare only three input terminals for inputting the - data T DATA and the test enable signal TE.

In the principle diagram showing the configuration of the LSi test method of the present invention, (2) is an LSi logic circuit with deep logic that requires a large number of clocks or patterns to be input to the input terminal In before changing the output signal of the output terminal Out. The logic circuits 11 to 1m+ are divided into a fixed number m+1 of logic circuits 11 to 1m+ according to function, and each division part has a test circuit 21 to 2m according to function, which inputs the input clock CK of the front stage circuit 11 as it is to the clock terminal of the rear stage circuit 12. This is an actual circuit of an LSi circuit provided with a certain number m.

3) Input test data T DATA for each function of the actual circuit l of the LSi circuit, and use the test clock T CLK to determine the number of circuits m of the two series of test circuits 21 to 2m.
A shift I register 31 that is shifted by a number of stages M equal to
This is a test signal generating section consisting of a gate 32 that selects and outputs m test data T DATA for each function.

Then, the test signal outputs TO to Tm-, which are the number m of parallel outputs of the gates 32 of the test signal generating section 3, are configured to be supplied to the functional test circuits 21 to 2m of the actual circuit 1 of the LSi circuit.

[Effect]

The actual circuit 1 of the 1.3i circuit is an LSi logic circuit with deep logic that requires many clocks or patterns to be input to the input terminal In before changing the output signal of the output terminal Out, and is designed according to the required functions. It is divided into a certain number of m+1 logic circuits 11 to 1m+1, and a pre-stage circuit 11 is installed at each divided point.
A certain number m of test circuits 21 to 2m are built-in, which input the input clock CK of 1 to the clock terminal of the subsequent stage circuit 12 as is.

The shift register 31 with m shift stages of the test signal generating section 3 of the LSi test method of the present invention has test data TDA.
Input TA and test clock T C input at the same time
By LK, the actual circuit 1 of the LSi circuit is shifted by the number of stages m equal to the number of circuits m of the built-in test circuits 21 to 2m, and outputs m parallel shift outputs 0 to m1, and is composed of m elementary gates. Output to gate 32.

The gate 32 gate-processes the parallel number m of shift outputs 0 to m-1 from the shift register 31 using the test enable signal TE input during testing, selects a designated shift output, and selects the designated shift output to apply the gate processing to the actual circuit 1 of the LSi circuit. Functional test circuit 2
Supply to 1-2m.

And test circuits 21 to 2m of the actual circuit 1 of the LSi circuit.
is the test ■,,j where the test enable signal TE is input
In step 7, the input clock CK of the front-stage circuit 11 at each divided point of the actual circuit 1 is inputted directly to the clock terminal of the rear-stage circuit 12, and the front-stage circuit 11 and the rear-stage circuit 12 are tested simultaneously using the same input clock CK.

Then, the transfer register 31 of the test signal generating section 3 converts the input test data T DATA into a number of stages m equal to the number m of test circuits 21 to 2 m included in the actual circuit 1 of the LSi circuit, using the test clock T CLK. The shift output 0=m-1 of the parallel parts is sent to the gate 32 by
The gate 32 gate-processes the outputs of the parallel number m from the shift register 31 using the test enable signal TE, and sends the processing results as test signals in parallel to m functional test circuits 21 to 2m. Since L
The functions of the actual circuit 1 of the Si circuit are diversified and the test circuit 21
Even if the number of circuits m increases by ~2m, the number of test signals input to the LSi circuit for testing, that is, the number of test terminals that should be installed in the LSi circuit, is the test clock T C
The problem is solved because it is sufficient to prepare only one set of three test terminals for inputting LK, test data T_DATA, and test enable signal Tli.

〔Example〕

FIG. 2 is a block diagram showing the configuration of the LSi test method of the present invention, and FIG. 3 is a time chart for explaining its operation.

In FIG. 2, the actual circuit 1 of the LSi circuit has an output terminal O
It is an LS+ circuit of a multi-stage counter with deep logic that requires a large number of clocks CK input to the input terminal In before changing the output signal of ut, and a fixed number m+1 is required for each required function.
The counters 11 to 1m (divided into 1, the input clock CK of the front stage counter 11 is inputted to each division point as is, and the clock terminal of the rear stage counter 12 (test circuit 2 inputted to J)
A certain number of meters of 1 to 2 meters are built-in.

The shift register 31 of the test signal generation unit 3 is composed of m cascaded D flip-flops FF l to FF m, and converts the input test data T DATA into the actual circuit of the LSi circuit using the test clock T CLK. The number of stages m is equal to the number of stages m of the test circuits 21 to 2m built in 1.
+3 sequential shift l-, m D flip-flops F
The parallel number m of Schiff I outputs oxli-, are outputted to the gate 32 from each 0 output terminal of Fl to FFm.

Gate 32B is a solid NAND game □NANrlo
・-NANDr)m, each NAND output of the parallel number m of the outputs of the shift register 31 is connected to one input terminal of each of the NANDm, and the test output is connected to the other input terminal. By manually inputting a signal with the polarity of the enable signal TE and a signal with the polarity inverted, the eggplant 1-enable signal TF,
During a test in which the polarity of 7 is inverted and a signal "L" is input, each shift output of the soft resistor 31 is NANDed by the test enable signal TE, and m outputs T are generated. -T
m- is selected and supplied as a test signal output to the functional test circuits 21 to 2+11 of the actual circuit 1 of the LSi circuit.

In time chart 1 in Figure 3, ■T CLK is
m D flip-flops FF] to FFm of the shift I register 31 of the test signal generating section 3.
LK, ■T DATA is test data T DATA that is input at the rising edge of the clock of ■T CLK and is finally supplied to m function-specific test circuits 21 to 2m of the actual circuit 1. It is. And, ■Test data T DATA is m D-flops of the shift register 31.

It is first input to the D input terminal of the first stage FF 1 of the flops FF 1 to FF m, and is outputted from its 0 output terminal to the first stage NANDo of the gate 32 as a -0 shift output 0. It is input to the D input terminal. Then, from the output terminal of the next stage FF 2 to the second stage NA of the gate 32
It is outputted to the NDI as a shift output 1 of -1, and at the same time is inputted to the D input terminal of the next third stage FF3.

Similarly, the shift outputs 0 to m-1 of the parallel number m of ■-0 to ■-m-1 are individually transferred from the m D flip-flops FF 1 to FF m of the shift register 31 to the gate 3.
2 m Nant gates NAND o~NORm-+
is output to one input terminal of

■TE, "L" is inverted in polarity by the inverter INV and connected to the m NAND gates of the gate 32.
The NAND signal of the gate 32 of the test signal generating section 3 is inputted to the other input terminal of NANDin-, and is supplied to the intermediate test circuit of the logic circuit to be tested among the test circuits 21 to 2m of the multi-stage counter of the actual circuit 1. Let the sign of the output of the gate NAND be "'L".

The sign "L" of the output T1 of NAND ] is changed to "L" by the inverter 224 of the second test circuit 22 of the actual circuit 1.
The clock input to the clock input terminal CK of the counter of the logic circuit 12 at the previous stage is directly inputted to the AND gate 221 by the AND gate 221 and the NOR gate 223. The operation of the counter of the next stage logic circuit 1m is tested using the clock input to the clock input terminal CK of the counter of the previous stage logic circuit 12.

As described above, the embodiment shown in FIG. 2 is based on the actual circuit 1 of the LSi circuit.
The test I/circuits 21 to 2m select and input the test signal output To"Tm-+ generated in the test signal generator 3 by the code "L" of the test enable signal TE during testing, and The input clock CK of the front-stage circuit 11 at the split point is directly applied to the clock terminal of the rear-stage circuit 12, and the tests of the front-stage circuit 11 and the rear-stage circuit 12 are performed simultaneously using the same input clock (J).

Then, the shift register 31 of the test signal generating section 3 converts the input test data T DATA into test data r, 1
T CLK outputs to the gate 32 as m parallel shift outputs equal to the number of stages m of the test I/circuits 21 to 2m built in the actual circuit 1 of the LSi circuit.
2 selects the shift outputs of the parallel number m of shift registers 31 by the test enable signal TE, and becomes L.

Since the actual circuit 1 of the Si circuit is supplied to the test circuits 21 to 2m for each function, even if the functions of the actual circuit 1 of the LSi circuit are diversified and the number m of the test circuits 21 to 2m increases, it can be used for testing. The number of test signals input to the LSi circuit, that is, the number of test terminals to be installed in the LSi circuit, is determined by the test clock T CLK and the data T DATA
There is no problem because it is sufficient to prepare only three test terminals for inputting the test enable signal TE and the test enable signal TE.

〔Effect of the invention〕

As explained above, according to the present invention, the LS
The number of test terminals to be provided in the i circuit is only three test terminals that input the test clock T CLK, test data T DATA, and test enable signal TE, so the actual circuit of the LSi circuit Even if the number of test circuits M increases due to the diversification of the functions of the LSi circuit, the number of test terminals connected to the outside can remain the same, and the number of internal wirings of the LSi circuit can be simply increased. This has the effect of avoiding cost increases associated with integration.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram showing the configuration of the LSi test method of the present invention, Fig. 2 is a block diagram showing the structure of the LSi test method of the embodiment of the present invention, and Fig. 3 explains the operation of the embodiment of the present invention. FIG. 4 is a block diagram of a conventional LSi test method. In the figure, 2 is an actual circuit, 3 is a test signal generator, 11 to 1m+1 are logic circuits, 21 to 2m are test circuits, 31 is a shift register, and 32 is a gate. 41 q -ノ \ノ \J \to

Claims (1)

[Claims] The input clock (CK) of the preceding stage circuit (11) is directly connected to the clock terminal of the succeeding stage circuit (12) by dividing it into a fixed number of logic circuits (11 to 1 m_+_1) according to function and testing each divided part. In an LSi test circuit that is tested by providing a certain number of input test circuits (21 to 2 m), the LSi
A shift in which the input of test data (TDATA) for each function of the test circuit is shifted by the number of stages m equal to the number of inserted circuits m of the test circuit (21 to 2m) using the test clock (TCLK) and output in parallel. A test signal generation unit consisting of a register (31) and a gate (32) that gate-processes a certain number m of parallel shift outputs of the shift register using a test enable signal (TE) input during testing, selects and outputs them. (3) is provided, and the test signal generating section (3) is provided.
) selected output signal (To
-Tm_-_1) is supplied to the test circuit (21-2m) for testing.