JPH0267765A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0267765A JPH0267765A JP22010688A JP22010688A JPH0267765A JP H0267765 A JPH0267765 A JP H0267765A JP 22010688 A JP22010688 A JP 22010688A JP 22010688 A JP22010688 A JP 22010688A JP H0267765 A JPH0267765 A JP H0267765A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion region
- type diffusion
- region
- oxide film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 238000009413 insulation Methods 0.000 claims description 2
- 238000005192 partition Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に高耐圧ＭＯ３型トラン
ジスタを有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a high breakdown voltage MO3 type transistor.
従来、この種の高耐圧ＭＯ３型トランジスタを有する半
導体装置は、第２図に示すように、Ｐ型シリコン基板１
の主表面に設けたＮ−型拡散領域２及びＮ−型拡散領域
２内に設けたＮ＋型拡散領域９によりドレイン領域を形
成し、ゲート電極７とＮ＋型拡散領域９との間には、膜
厚の厚い酸化膜１３を介在させていた。このようにＮ＋
型拡散領域９をゲート電極７から隔て、更にＮ＋型拡散
領域９の不純物濃度をコントロールすることにより、ゲ
ート電極７、ソース領域８及びＰ型シリコン基板１のそ
れぞれを接地した状態で前記ドレイン領域に電圧を印加
したときの耐電圧（以後ＯＦＦ耐圧と記す）はゲートの
絶縁破壊電圧以上に上げることが可能となった。Conventionally, a semiconductor device having this type of high-voltage MO3 type transistor has a P-type silicon substrate 1, as shown in FIG.
A drain region is formed by an N- type diffusion region 2 provided on the main surface of the N- type diffusion region 2 and an N+ type diffusion region 9 provided within the N- type diffusion region 2, and between the gate electrode 7 and the N+ type diffusion region 9, A thick oxide film 13 was interposed. Like this N+
By separating the type diffusion region 9 from the gate electrode 7 and further controlling the impurity concentration of the N+ type diffusion region 9, the gate electrode 7, the source region 8, and the P type silicon substrate 1 are each connected to the drain region while being grounded. It has become possible to increase the withstand voltage (hereinafter referred to as OFF withstand voltage) when a voltage is applied to be higher than the dielectric breakdown voltage of the gate.
上述した従来の半導体装置は、ゲート電極とＮ＋型拡散
領域との間のＮ−型拡散領域の表面に厚い酸化膜を介在
させることにより、トランジスタのＯＦＦ耐圧の向上は
可能であったものの、電流駆動能力（以下ＯＮ電流と記
す）が非常に低くなってしまうという問題点を有してい
る。In the conventional semiconductor device described above, although it is possible to improve the OFF breakdown voltage of the transistor by interposing a thick oxide film on the surface of the N- type diffusion region between the gate electrode and the N+ type diffusion region, the current The problem is that the driving ability (hereinafter referred to as ON current) becomes extremely low.
また、ＬＳＩの出力トランジスタとして用いる時には、
所望の電流量に対してトランジスタのゲート幅を大きく
して対処する必要があり、このような出力端子が非常に
多い時には、これにより半導体チップの寸法が増大する
という問題も生じる。Also, when used as an LSI output transistor,
It is necessary to increase the gate width of the transistor to cope with the desired amount of current, and when there are a large number of such output terminals, this also causes the problem of increasing the size of the semiconductor chip.
また、厚い酸化膜下にＮ型不純物を高濃度に自己整合的
に導入して、この寄生抵抗を低減しようとすると、ゲー
ト電極下へＮ型の高濃度不純物層ができることになり、
トランジスタのＯＦＦ耐圧の低下を招くという問題点が
ある
本発明の目的は、ＯＦＦ耐圧が高く且つ電流駆動能力の
すぐれた半導体装置を提供することにある。Furthermore, if an attempt is made to reduce this parasitic resistance by introducing N-type impurities at a high concentration under a thick oxide film in a self-aligned manner, an N-type high concentration impurity layer will be formed under the gate electrode.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a high OFF breakdown voltage and excellent current driving ability, which has the problem of lowering the OFF breakdown voltage of a transistor.
〔課題を解決するための手段〕
本発明の半導体装置は、−導電型半導体基板の主表面に
設けた逆導電型のドレイン領域形成用の低濃度拡散領域
と、前記低濃度拡散領域の表面に設けた凹部の底面に設
けた逆導電型の高濃度拡散領域と、前記凹部内部に充填
して設けた埋込絶縁膜と、前記半導体基板の表面に設け
て前記埋込絶縁膜を含む素子形成領域を区画するフィー
ルド絶縁膜と、前記素子形成領域の表面に設けたゲート
絶縁膜と、前記埋込絶縁膜の一部を含み前記ゲート絶縁
膜上に設けたゲート電極と、前記ゲート電極に整合して
前記素子形成領域に設けた逆導電型のソース領域と、前
記埋込絶縁膜に隣接して前記低濃度拡散領域内に設けた
逆導電型の高濃度拡散領域とを有する。[Means for Solving the Problems] A semiconductor device of the present invention includes a low concentration diffusion region for forming a drain region of the opposite conductivity type provided on the main surface of a -conductivity type semiconductor substrate, and a low concentration diffusion region provided on the surface of the low concentration diffusion region. Forming an element including a high concentration diffusion region of opposite conductivity type provided on the bottom surface of the provided recess, a buried insulating film provided filling the inside of the recess, and the buried insulating film provided on the surface of the semiconductor substrate. A field insulating film that partitions a region, a gate insulating film provided on the surface of the element formation region, a gate electrode provided on the gate insulating film including a part of the buried insulating film, and a gate electrode that is aligned with the gate electrode. and a source region of opposite conductivity type provided in the element forming region, and a high concentration diffusion region of opposite conductivity type provided in the low concentration diffusion region adjacent to the buried insulating film.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を説明するための半導体チッ
プの断面図である。FIG. 1 is a sectional view of a semiconductor chip for explaining one embodiment of the present invention.
図に示すように、Ｐ型シリコン基板１の主表面に低濃度
のリンイオンを選択的にイオン注入して熱処理し、不純
物濃度がｌＸｌ０”〜５Ｘ１０７Ｃｍ−３の範囲内にあ
るドレイン領域形成用のＮ−型拡散領域２を設ける。次
に、Ｎ−型拡散領域の表面を選択的にエツチングして凹
部を設け、前記凹部底部に高濃度のヒ素イオンをイオン
注入してＮ＋型拡散領域３を設ける。次に、前記凹部を
含む表面にＣＶＤ法により酸化シリコン膜を堆積した後
全面を異方性エツチングして前記酸化シリコン膜の上面
をちょうどＮ−型拡散領域を含むＰ型シリコン基板１の
表面と一致させた埋込酸化膜４を形成する。次に、Ｐ型
シリコン基板１の表面を選択的に酸化したフィールド酸
化膜５を設けて素子形成領域を区画し、前記素子形成領
域の表面にゲート絶縁膜６を形成する。次に、埋込酸化
膜４の一部を含むゲート絶縁膜６の上に選択的にゲート
電極７を設け、ゲート電極７に整合させて前記素子形成
領域にＮ型の高濃度不純物を導入しソース領域８及び埋
込酸化膜４に隣接してＮ−型拡散領域２の中にＮ＋型拡
散領域９を設ける。次に、ゲート電ｇ＋７を含む表面に
眉間絶縁膜１０を堆積し、ソース領域８及びドレイン領
域のＮ＋型拡散領域９のコンタクト用開孔部をそれぞれ
設け、前記開孔部のソース領域８及びＮ＋型拡散領域９
のそれぞれと接続するアルミニウム電極１１．１２を形
成して高耐圧ＭＯＳ型トランジスタを有する半導体装置
を構成する。As shown in the figure, low-concentration phosphorus ions are selectively implanted into the main surface of a P-type silicon substrate 1 and heat-treated to form a drain region with an impurity concentration of 1X10'' to 5X107Cm-3. A - type diffusion region 2 is provided.Next, the surface of the N- type diffusion region is selectively etched to form a recess, and arsenic ions of high concentration are implanted into the bottom of the recess to provide an N+ type diffusion region 3. Next, a silicon oxide film is deposited on the surface including the recessed portions by the CVD method, and then the entire surface is anisotropically etched so that the upper surface of the silicon oxide film is formed exactly on the surface of the P-type silicon substrate 1 including the N-type diffusion region. Next, a field oxide film 5 is formed by selectively oxidizing the surface of the P-type silicon substrate 1 to define an element formation region, and a buried oxide film 4 is formed to match the surface of the element formation region. A gate insulating film 6 is formed.Next, a gate electrode 7 is selectively provided on the gate insulating film 6 including a part of the buried oxide film 4, and N is aligned with the gate electrode 7 in the element formation region. type high-concentration impurities are introduced into the N- type diffusion region 2 adjacent to the source region 8 and the buried oxide film 4.N+ type diffusion region 9 is then formed in the N- type diffusion region 2.Next, glabellar insulation is formed on the surface containing the gate voltage g+7. A film 10 is deposited, contact openings are provided for the source region 8 and the N+ type diffusion region 9 of the drain region, respectively, and the source region 8 and the N+ type diffusion region 9 of the opening are provided.
Aluminum electrodes 11 and 12 are formed to be connected to each of the two to form a semiconductor device having a high voltage MOS transistor.
ここで、ゲート電極７とＮ１型拡散領域９との間は、埋
込み酸化膜４で隔てられているため、ゲートとドレイン
間のＭＯＳ型トランジスタのＯＦＦ耐圧を充分高く維持
するとともに、ドレインの寄生抵抗値を減少させるため
に埋込み酸化膜４の下面に設けなＮ＋型拡散領域３によ
り電流駆動能力のすぐれた高耐圧ＭＯＳ型トランジスタ
が得られる。Here, since the gate electrode 7 and the N1 type diffusion region 9 are separated by the buried oxide film 4, the OFF breakdown voltage of the MOS transistor between the gate and the drain can be maintained sufficiently high, and the parasitic resistance of the drain can be maintained. By providing the N+ type diffusion region 3 on the lower surface of the buried oxide film 4 in order to reduce the voltage, a high breakdown voltage MOS type transistor with excellent current driving ability can be obtained.
〔発明の効果〕
以上説明したように本発明は、ドレイン領域を構成する
Ｎ−型拡散領域内に設けた埋込み酸化膜と埋込み酸化膜
の下面に設けなＮ＋型拡散領域によりＮ＋型拡散領域と
ゲート電極とを隔てることにより、トランジスタのＯＦ
Ｆ耐圧を確保すると共に、高耐圧化したことによりＯＮ
電流の低下を埋込み酸化膜の下面に設けたＮ＋型拡散領
域によりドレインの寄生抵抗を低減させることが可能と
なり、駆動能力のより大きな高耐圧ＭＯ３型トランジス
タを有する半導体装置を実現できるという効果がある。[Effects of the Invention] As explained above, the present invention has a buried oxide film provided in the N- type diffusion region constituting the drain region and an N+ type diffusion region provided on the lower surface of the buried oxide film to form the N+ type diffusion region. By separating the gate electrode, the OF of the transistor
In addition to securing the F withstand voltage, it is ON due to the high withstand voltage.
The N+ type diffusion region provided on the bottom surface of the buried oxide film makes it possible to reduce the parasitic resistance of the drain, which has the effect of realizing a semiconductor device having a high breakdown voltage MO3 transistor with greater drive capability. .
第１図は本発明の一実施例を説明するための半導体チッ
プの断面図、第２図は従来の半導体装置の一例を説明す
るための半導体チップの断面図である。
１・・・Ｐ型シリコン基板、２・・・Ｎ−型拡散領域、
３・・・Ｎ＋型拡散領域、４・・・埋込酸化膜、５・・
・フィールド酸化膜、６・・・ゲート絶縁膜、７・・・
ゲート電極、８・・・ソース領域、９・・・Ｎ＋型拡散
領域、１０・・層間絶縁膜、１１．１２・・・アルミニ
ウム電極、１３・・・酸化膜。
万FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor chip for explaining an example of a conventional semiconductor device. 1... P type silicon substrate, 2... N- type diffusion region,
3... N+ type diffusion region, 4... Buried oxide film, 5...
・Field oxide film, 6... Gate insulating film, 7...
Gate electrode, 8... Source region, 9... N+ type diffusion region, 10... Interlayer insulating film, 11.12... Aluminum electrode, 13... Oxide film. Ten thousand
Claims (1)
イン領域形成用の低濃度拡散領域と、前記低濃度拡散領
域の表面に設けた凹部の底面に設けた逆導電型の高濃度
拡散領域と、前記凹部内部に充填して設けた埋込絶縁膜
と、前記半導体基板の表面に設けて前記埋込絶縁膜を含
む素子形成領域を区画するフィールド絶縁膜と、前記素
子形成領域の表面に設けたゲート絶縁膜と、前記埋込絶
縁膜の一部を含み前記ゲート絶縁膜上に設けたゲート電
極と、前記ゲート電極に整合して前記素子形成領域に設
けた逆導電型のソース領域と、前記埋込絶縁膜に隣接し
て前記低濃度拡散領域内に設けた逆導電型の高濃度拡散
領域とを有することを特徴とする半導体装置。A low concentration diffusion region for forming a drain region of the opposite conductivity type provided on the main surface of a semiconductor substrate of one conductivity type, and a high concentration diffusion region of the opposite conductivity type provided at the bottom of a recess provided on the surface of the low concentration diffusion region. a buried insulating film filled in the recess, a field insulating film provided on the surface of the semiconductor substrate to partition an element formation region including the buried insulating film, and a field insulation film provided on the surface of the element formation region. a gate insulating film provided, a gate electrode including a part of the buried insulating film and provided on the gate insulating film, and a source region of an opposite conductivity type provided in the element formation region in alignment with the gate electrode; . A semiconductor device comprising: a high concentration diffusion region of an opposite conductivity type provided in the low concentration diffusion region adjacent to the buried insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63220106A JP2712359B2 (en) | 1988-09-01 | 1988-09-01 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63220106A JP2712359B2 (en) | 1988-09-01 | 1988-09-01 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0267765A true JPH0267765A (en) | 1990-03-07 |
| JP2712359B2 JP2712359B2 (en) | 1998-02-10 |
Family
ID=16746007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63220106A Expired - Lifetime JP2712359B2 (en) | 1988-09-01 | 1988-09-01 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2712359B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5632111A (en) * | 1992-09-01 | 1997-05-27 | Daiwa Seiko, Inc. | Fishing rod with reel fastener |
| US5984847A (en) * | 1994-08-16 | 1999-11-16 | Beloit Technologies, Inc. | Self loading controlled deflection roll |
| JP2002170888A (en) * | 2000-11-30 | 2002-06-14 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
| JP2008504680A (en) * | 2004-06-23 | 2008-02-14 | フリースケール セミコンダクター インコーポレイテッド | LDMOS transistor |
| JP2008258640A (en) * | 2008-05-07 | 2008-10-23 | Renesas Technology Corp | Semiconductor integrated circuit device |
| KR100953014B1 (en) * | 2006-11-30 | 2010-04-14 | 가부시끼가이샤 도시바 | Semiconductor device and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6453574A (en) * | 1987-08-25 | 1989-03-01 | Mitsubishi Electric Corp | Semiconductor device |
-
1988
- 1988-09-01 JP JP63220106A patent/JP2712359B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6453574A (en) * | 1987-08-25 | 1989-03-01 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5632111A (en) * | 1992-09-01 | 1997-05-27 | Daiwa Seiko, Inc. | Fishing rod with reel fastener |
| US6374534B1 (en) | 1992-09-01 | 2002-04-23 | Daiwa Seiko, Inc. | Fishing rod with reel fastener |
| US5984847A (en) * | 1994-08-16 | 1999-11-16 | Beloit Technologies, Inc. | Self loading controlled deflection roll |
| JP2002170888A (en) * | 2000-11-30 | 2002-06-14 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
| US7541661B2 (en) | 2000-11-30 | 2009-06-02 | Renesas Technology Corp. | Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs |
| US7790554B2 (en) | 2000-11-30 | 2010-09-07 | Renesas Technology Corp. | Method of manufacturing semiconductor integrated circuit device with high and low breakdown-voltage MISFETs |
| JP2008504680A (en) * | 2004-06-23 | 2008-02-14 | フリースケール セミコンダクター インコーポレイテッド | LDMOS transistor |
| KR100953014B1 (en) * | 2006-11-30 | 2010-04-14 | 가부시끼가이샤 도시바 | Semiconductor device and manufacturing method thereof |
| US7709906B2 (en) | 2006-11-30 | 2010-05-04 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| JP2008258640A (en) * | 2008-05-07 | 2008-10-23 | Renesas Technology Corp | Semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2712359B2 (en) | 1998-02-10 |
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