JPH0267955A - Synthetic aperture processing apparatus - Google Patents

Abstract

PURPOSE:To diagnose the functions of each circuit associated with regeneration processing or the normal property of the data flow between parts by providing switches, first and second ROMs for a test mode, a reading circuit, a judging circuit and the like. CONSTITUTION:When a test mode is selected with a switch SW1, data are transferred into an A/D memory 5 from a first ROM 14. Data which can confirm the function of each part associated with regeneration processing and normal property of data transfer between parts are stored in the first ROM 14. Said data in the memory 5 are further shifted into a second RAM (waveform memory) 6. Meanwhile, the data which are read out of the memory 6 are added in accordance with a test address which is transferred into a third RAM 9 from a second ROM 15 for a test mode. The result is stored in a fourth RAM (memory for storing the result of regeneration) 10. When an arbitrary address in the memory 10 is instructed from the outside, the content of the instructed address is read with a reading circuit 17 and compared with a judging value in a judging circuit 18. Thus the pass or fail is judged. As a result, the reliability of the apparatus can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is a non-destructive technology that can detect defects in metal materials using ultrasonic waves, for example, and display images of the defects in high resolution and in real time. This invention relates to a synthetic aperture processing device using a synthetic aperture radar that can visualize the ground surface situation from above using electromagnetic waves.

[Conventional technology]

One of the methods used in ultrasonic non-destructive testing, etc., narrows down the ultrasonic beam and measures the spatial information of a single point on the object to be reproduced based on the propagation time from transmission to reception of the reflected signal.
The ultrasonic transmitter/receiver is sequentially scanned electrically or mechanically,
In contrast to the method of visualizing and displaying the object image to be reproduced as a collection of point information, this method irradiates the object with a spread ultrasonic beam.

There is a so-called synthetic aperture method in which the reflected wave or transmitted wave is received by a receiving element, the amplitude and phase information of the wave is combined (hologram creation), and an object image is reconstructed from this hologram. In principle, this method has the characteristic that the resolution remains constant regardless of the distance to the object.

FIG. 3 shows a conventional example of a synthetic aperture processing apparatus that performs regeneration processing of an object using an ultrasonic synthetic aperture method.

In the figure, (1) is an ultrasonic transceiver (hereinafter referred to as a transceiver), (2) is a transmitter, [31 is a receiver, and (4) is an A/
D converter, (6) is a first RAM (hereinafter referred to as A/D memory for convenience of explanation), ts) is a second RAM (hereinafter referred to as waveform memory), 171 is a latch gate circuit, and (B1 is an adder).

(91 is the third RAM that stores the focus table (
113 is a scanning drive mechanism, and 19 is the material to be tested. The waveform memory 161 is a memory I with address length N.
The A/D memo (Jan. 5) consists of one memory with address length N, AIh.

Furthermore, the playback result memory + IG also consists of one memory with address length N, that is, Pl. A conceptual diagram of memories AD and Pl is shown.

Further, FIG. 5 is a diagram for explaining the principle of reproduction processing using the 9-synthetic aperture method.

In the figure, the horizontal axis represents the scanning direction of the transmitter/receiver, the vertical axis represents time, and To represents the time of transmission.

Now, the received signal at each scanning point containing the information of point a to be reproduced has a phase lag corresponding to the distance between each scanning point and point a, and the trajectory of the phase lag is as shown in the figure. It becomes a hyperbola with a apex. In addition, the range in the scanning direction in which a received signal containing the information of two points a can be obtained is determined by the spread of the ultrasonic beam, and the maximum range in the scanning direction that can receive the point information at the maximum distance in the depth direction to be reproduced is determined by the spread of the ultrasonic beam. The range is called the synthetic aperture length and is represented by L in Figure 2. In order to reproduce point a in Fig. 2, the received signals at each scanning point regarding the two points a in the synthetic aperture length range are added along the previous two-phase locus (hereinafter referred to as the two-phase history line). become.

Furthermore, FIG. 6 is a diagram for explaining the configuration of the waveform memos IJM, -MM.

In the figure, the horizontal axis corresponds to the scanning direction, and the vertical axis corresponds to the depth direction. Ll and Ll are the synthetic aperture ranges based on the synthetic aperture length, and /1 and 12 are the synthetic aperture ranges L1.
and the playback target #! played by Ll! (hereinafter referred to as the target line), and 1, 2, 3. ...... (M-1).

M, (M+1) are two scanning points a and point a are points in the same depth direction and are also points on the object lines 11 and 12.

The received signal obtained corresponding to each scanning point is A/D converted at a predetermined sampling period by the A/D & converter (4), and when one synthetic aperture range L1 has been scanned from scanning point 1 to M. 2M discrete digital value sequences are obtained for the number of scanning points.

Therefore, the number M of the waveform memories M1 to MM is.

This corresponds to the number of scanning points within the synthetic aperture range.

Further, the address length N corresponds to the number of discrete digital values.

The procedure for reproducing one point a is as follows: 11) Store the discrete digital value sequences obtained at scanning points 1 to M within the synthetic aperture range L1 in the waveform memories M1 to MM in correspondence with each scanning point. (2) Necessary data determined by the phase history line from the discrete digital value string at each scanning point for reproducing point a is extracted and added.

The necessary data determined from the phase history line in the discrete digital value sequence at each scanning point for reproducing the two points a can be retrieved from the waveform memories M1 to MM by the following method. In other words, address values in the waveform memories M1 to MM in which necessary discrete digital signals are stored are set at each scanning point, that is, in accordance with the phase history line uniquely defined corresponding to the point to be reproduced. A table is created in correspondence with the memory, and this table, that is, the table memo 1
According to the address information from May 91, the waveform memo 'JM
A plurality of discrete digital values corresponding to the point to be reproduced are read from h to MM and transferred to the adder (81).

Next, K for reproducing point a' is determined by the phase history line for two points a' out of the discrete digital value sequence of each received signal obtained at each scanning point 2 to (M+1) in the front P synthetic aperture range L2. The plurality of discrete digital values read from the waveform memories M1 to MM are similarly added based on the address information of the table memory (9).

As described above, the fact that the target line is sequentially shifted in the scanning direction means that the data in the waveform memories M1 to MM operate as follows. That is, the previous lid (
After obtaining the received signal for one line at the (M+1) scanning point, the discrete digital values for one line at the (M+1) scanning point are transferred from the A/D memory AD1 to the waveform memory M.
When storing in MM of 1 to MM, the waveform memory M
The discrete digital value string stored in 1 to MM is line-shifted one line at a time, and the data for one line at the scanning point 1 is discarded. The data for one line at (M+1) is stored in the line where the data for one line at (M+1) was stored. Note that the above line shift operation is performed by the latch gate circuit (71) every time the transmitter/receiver (1) is scanned.
will do it.

By the way, if the depths of point a and point a' are the same, the 1-phase history lines will also be the same, therefore.

The addresses in the waveform memories M1 to MM of data necessary to reproduce points having the same depth are also the same. That is, the focus table stored in the table memory (9) based on the phase history line uniquely determined corresponding to a certain depth can be commonly used for points at the same depth in different synthetic aperture ranges. can.

To summarize each operation above, the operation for one scanning question is as follows.

(2) A transmission pulse is applied from the transmitter (2) to the transmitter/receiver (1). ■The received signal is from the A/DK converter (4)
is converted into a discrete digital value, and the discrete digital value string is stored in the A/D memory AD1.
/ D Memo IJ Data is transferred and stored from ADt. ■ Necessary data is read from each of the memories M1 to MM according to the address information of the table memo (January 9) and transferred to the adder (81). ■ The adder (8) reads each point to be reproduced. Addition processing is performed. ① Addition result in the adder [8], ie.

The data for one line in the depth direction is the playback result memo IJ.
This means that the data is transferred to Pl and one line of data is reproduced.

That is, each time the transmitter/receiver (1) is quantified, the above
The following actions are performed.

The regeneration control circuit 1υ is operated by the A/D converter (41) according to instructions from the timing control section α.
/ The timing control section 13 controls the timing from the D-converted received signal to the reproduction of one line, and also controls the timing of transmission, reception, reproduction, and image display.

Furthermore, FIG. 7 is a diagram for explaining the relationship between the waveform memory (61) and the table memo 91.

In the same figure, the table memory (9) has the same address length N as each of the waveform memos M1 to MM.
AM, that is, it consists of table memories F1 to FM, each corresponding to the waveform memories M1 to MM. For example, each of the table memories F1 to FM stores the address of data stored in each of the waveform memories M1 to MM necessary to reproduce a certain reproduction target point a, and Each of the waveform memories M1 to MMK is accessed simultaneously, M pieces of data are simultaneously read out, and the reproduction target point a is reproduced. ! If there are N target points on one line, the operation of simultaneously reading M data from the waveform memories M1 to MM for each of the eight points is repeated N times to reproduce one line.

On the other hand, as shown in FIG. 4 (cl), the reproduction result memory no is also a RAM P1 with an address length of N.

Each corresponds to N reproduction symmetry points on the center line of the synthetic aperture range to be reproduced.

Therefore, one line, that is, N pieces of digital data read out and reproduced from the e-waveform memories M1 to MM by repeating N times is stored in the reproduction result memory P1.

[Problem to be solved by the invention]

As explained in the section on the conventional device, the table memories F1 to FM store addresses based on the phase history of discrete digital values in the waveform memory necessary to reproduce a certain reproduction target point, and are used for reproduction processing. Sometimes, the waveform memories M1 to MM are accessed according to the addresses, for example.

Table memo IJF that stores the focus table
If a problem occurs in t-FM and a normal address is not stored, the result of adding the data read from the waveform memories M1-MM by the adder will not be a correct value.

Therefore, it becomes necessary to determine the normality of the reproduction processing section in terms of reliability of the device. By the way, after the A/D converter,
A/D memo IJ AD1# waveform memory M1 to MM p table memory F1 to FM m and the adder are a set of logic circuits, and data processing is a logical calculation of digital values. Therefore, if the contents of the data entering the A/D memory AD1 and the data in the table memories F1 to FM, that is, the contents of the algorithm of the addition process, are known, the reproduction result memo IJp as described above is known.

The contents of A/D memory AD1°, waveform memories M1 to MM, and table memories F1 to FM.

It is theoretically possible to determine the normality of the logic up to the adder, that is, whether or not the functions of each part and data transfer between each part are being performed normally. However, in reality, appropriate data is needed to confirm the normality of the functions of each part.
Conventionally, there has been no method that can test data into the A/D memory ADi and make the above-mentioned determination quickly and automatically while the device is in use.

For this reason, it has not been possible to improve the reliability of the reproduction results subjected to synthetic aperture processing.

This invention was made to solve such problems, and allows the user to select between a test mode and a normal flaw detection or inspection mode, and when in the test mode, the regeneration results can be predicted in advance, and each part related to the regeneration process can be checked. a first ROM that stores data that enables the test to be performed, and a second ROM that is provided to transfer address data in the waveform memory to a table memory that allows prediction of playback results. In mode, the data in the first ROM is transferred to the A/D memory and further shifted to the waveform memory.

According to an algorithm based on the address data stored in the second ROM, the previous P waveform memory is read out, added by the adder, and stored in the playback result storage memory, while the playback result storage memory By externally specifying an arbitrary address in the memory, the addition result within the specified address is compared with a predetermined judgment value in the judgment circuit, thereby improving the functions of each part involved in the playback process and data transfer between each part. You can check the normality of.

[Means to solve the problem]

The synthetic aperture processing device according to the present invention has a changeover switch for selecting a test mode and a normal flaw detection or inspection mode, and stores data that corresponds to checks of each part in advance and allows prediction of playback results. Furthermore, when the test mode is selected by the aforementioned changeover switch e.

A test mode ROM that can transfer data to the E'A/D memory, and address data for accessing the appropriate address in the waveform memory for the test mode, are used for testing. mode, a second ROM for test mode that transfers the address data to the table memory, an address switch for specifying the address of the memory for storing the previous 6e playback results, and a second ROM for the test mode that transfers the address data to the table memory; It is equipped with a readout circuit that reads data 1 from the memory for storing P reproduction results, and a determination circuit that compares the read data with a predetermined determination value and makes a determination.

[Effect]

In the synthetic aperture processing device according to the present invention, a test mode is selected by a changeover switch from a first ROM in which data is stored in advance to confirm the functions of each part involved in playback processing and the normality of data transfer between each part. When the data is transferred to the A/D memory and further shifted to the waveform memory, on the other hand.

According to the test address transferred from the second ROM for test mode to the table memory, the data read from the waveform memory is added and stored in the memory for storing recurrent results. By specifying an arbitrary address from the outside, the content of the specified address is read out and compared with a judgment value in a judgment circuit to judge whether it is correct or not, thereby improving the reliability of attachment.

〔Example〕

11) is an ultrasonic transceiver (hereinafter referred to as a transducer), +2+ is a transmitter, 13) is a receiver, (41 is an A/D converter, (5)
shi is the first RAM (hereinafter referred to as i!! A/D memory for convenience).

(61 is the second RAM (hereinafter referred to as waveform memo!J),
(71 is a latch gate circuit, (8) is an adder, +9)
is the third RAM that stores the focus table (hereinafter referred to as table memo IJ), +10 is the fourth RAM that stores the playback results (hereinafter referred to as playback result memo!J), and (lυ is the playback calculation control circuit (hereinafter referred to as table memo IJ).

(return control circuit), nz is a timing control section, <13 is a set meal drive mechanism, and u9 is a material to be inspected. The waveform memo January 6) has M memories of address length N, ie, M1 to MM.
It consists of m, front f! i”A/I)me%1Jts)
u7) 'One memory A/DlJ with address length N.Furthermore, the reproduction result memory +IQ also consists of one memory Rp and Pl with address length N.

Furthermore, SWl is a changeover switch, α4 is a test mode snack-17) HoM (hereinafter referred to as the first (i') ROM
), its is still the second ROM for test mode
(hereinafter referred to as the second ROM), SW2 is an address switch, Kasumi is an encoder for binarizing the address value instructed by the address switch 2, (171
sends the binarized value to the reproduction result memory P1,
There is also a readout circuit that sends a signal to put the reproduction result memory P1 into a readout mode, and US is a determination circuit in which a certain value is set in advance.Next, the characteristics of the synthetic aperture processing device of the present invention are as follows. The operation in the test mode will be described below with reference to FIG.

According to FIG. 2, the test mode is changed over by the switch s.
If w1 selects 9 normal operation, the above A
Instead of storing the digital value string from the /D converter (4), the first ROM fi41 and the A/D memory A
As shown in the figure (/') in D1, a digital value string in which only the first value is 1° and the others are 0 is stored.

This switching is performed by operating the selector S1 in response to a signal from the changeover switch SW1.

On the other hand, in normal operation, the focus table data is stored in the table memo 'J Fi to FM through the playback control circuit tllll (as shown in the figure, the first memory of each of the table memories F1 to FM is set to 0). Among them, 1024 data are transferred from the second ROM<1!9. In this case also, the changeover switch SW
Switching is performed by operating the selector S2 in response to the signals .

By the way, the second data in the reproduction result memory P1 is obtained by reading M pieces of data from each of the waveform memories M1 to MM accessed by the address value stored at the second address in each of the table memories F1 to FM. Served,
It is reproduced by adding in the adder (81).

Each time a periodic trigger pulse from a pulse generator (not shown) is sent to the timing control section,
From the A/D memo IJAD1 to the waveform memory M1~
Test data is input line by line to MM, for example, all data in the waveform memory MMKA/D memory AD is inputted to the waveform memory MMKA/D memory AD by the first trigger pulse, and transferred to the waveform memory by the second trigger pulse of the ninth order. The data of MM is shifted to the waveform memory M (M-1), and similarly the data of A/M is shifted to the waveform memory M (M-1).
All data in D memory AD is transferred to waveform memory MV. Therefore.

At the K-th (K≦M) trigger pulse, the waveform memory M
All the A/D memories AD1 from 1 to MM
test data will be stored.

On the other hand, each of the waveform memories M1 to MM has an address length of 1024
(0 address to 1023 address).
The address length of each of table memories F1 to FM is also 102
4, and the value 1024 stored in each address 1 to 1023 has no meaning.

That is, this means that the addresses of the waveform memories M1 to MM that fall are also not accessed. Therefore, table memory F1
The value OK stored at address 0 of each of the waveform memories M1 to MM is accessed from the value OK stored at address 0 of each of the waveform memories M1 to MM, and the result of their addition is stored in the same address O of the reproduction result memory P1, and the table memories F1 to FM are Since no data is read from each of the waveform memories M1 to MM due to the address value 1024 stored in addresses 1 to 1023 of each of
At address 1023, only 0 or the value before being cleared exists.

On the other hand, when looking up an address in the playback result memory P1, for example, if K is specified with the address switch SW2, the value υ is set to 2 by the encoder ne.
The readout circuit αη reads out the data from the address of the reproduction result memory P1, and the data is read out from the address of the reproduction result memory P1.
The normality of the data can be confirmed by comparing it with a preset determination value in seconds. For example, when counting up to the pulse generator, if the data in the A/D memory ADI has been shifted in normally by waveform memory MK, then the table memories F1 to FM
The addition result of the data read out should be the value K, but there happened to be a problem in the address data line between each of the waveform memories M1 to MM and each of the table memories F1 to FM. Waveform memory M
If the contents of the table memory px are not correctly transmitted to K, the addition result will only be the value (K-1). On the other hand, by designating Kt- with the address switch Sw2, the contents of the address are read out and compared with a determination value in the determination circuit US, and it is determined that the address is abnormal. In addition.

In the case of the upper dpi test mode, the waveform memories M1 to
Since the purpose is to test the address data line between each MM and each of the table memories F1 to FM, the first ROM 114 stores data with contents corresponding to that purpose.
It is necessary for the first and second ROM files to be provided. Furthermore, since the contents of the reproduction result memory P1 change every moment along with the count number of trigger pulses, it is necessary to include a circuit in the judgment circuit that counts the number of pulses in synchronization with the trigger pulses as a judgment value. be.

As described above, by storing data in the first ROM and second ROM in accordance with the purpose of the test, these data can be used to determine the functions of each part involved in playback processing and the data between each part. You can check the flow logically.

Incidentally, in this embodiment, there is only one 2-determination circuit for monitoring the address 011 of the reproduction result memory P1, but the determination circuit is provided to monitor a plurality of addresses of the reproduction result memory P1. It goes without saying that even if a plurality of determination circuits are provided and address switches and readout circuits are provided corresponding to the plurality of determination circuits, the same effects as the present invention can be achieved.

〔Effect of the invention〕

As described above, the synthetic aperture processing device according to the present invention includes the second ROM for the A/D memory and the second ROM for the table memory, which store data with contents according to the purpose of the test. In the test mode, data is transferred from each ROM to the A/D memory and the table memory, added according to the P2 capacity of the table memory in the test mode, and stored in the playback result storage memory. By specifying an arbitrary address in the storage memory from the outside, the contents of that address are read out and compared with the judgment value in the judgment circuit to judge the normality of the addition result. It is possible to diagnose the normality of the function or data flow between each part, and to test the regeneration processing part of the device quickly and automatically even while the device is in use, improving the reliability of the device. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the synthetic aperture processing apparatus according to the present invention, FIG. Diagrams showing a conventional synthetic aperture processing device, Fig. 4 (al, (b)
l and (cl are respectively the second RAM and the first RA equipped with the present invention or the conventional synthetic opening processing bag fI!/c
FIG. 5 is a diagram for explaining the N principle of synthetic aperture processing. FIG. 6 is a diagram for explaining the principle of construction of the second RAM included in the synthetic aperture processing device of the present invention or the prior art, and FIG. It is a diagram showing the relationship between the second frame W and the third RAM, in which (1) is an ultrasonic transceiver, 121 is a transmitter, (3
) is the receiver, and (4) is the A/D converter. (5) is the first RAM, 16+ is the second RAM, +
71 is a latch gate circuit, (81 is an adder, (91 is a third RAM, (11) is a fourth RAM, luml is a reproduction arithmetic control circuit, aa is a first ROM, (19 is a second ROM) , +lη is a readout circuit, aS is a determination circuit, gWl is a changeover switch, and sw2 is an address switch. Note that the same or equivalent parts in Figure 1 are indicated with the same reference numerals. Figure 2 (a) (b)

Claims (1)

[Claims] A transceiver that generates and detects ultrasonic waves or electromagnetic waves,
a transmitter that applies an electrical signal to the transceiver; and a transmitter that mechanically or electronically scans the transceiver to transmit a spatially spread ultrasonic or electromagnetic wave beam into the interior of the target object at each scanning point in the scanning direction. A receiver that receives reflected waves from inside the target object of the ultrasonic or electromagnetic wave beam detected by the transceiver as a result of the transmission, and converts the received signal corresponding to the scanning point from the receiver from analog to digital. an A/D converter, a first RAM that stores a plurality of discrete digital values corresponding to one scanning point obtained by the A/D converter, and one scanning point from the first RAM; a second RAM configured in a two-dimensional frame memory to sequentially receive a plurality of discrete digital values corresponding to each scan for each scan and store the plurality of discrete digital values corresponding to the scanning points as a sequence of discrete digital values corresponding to the scanning points; , when the received signal of the latest scanning point is obtained, all the discrete digital value strings in the second RAM in which the discrete digital value strings up to the scanning point immediately before the latest scanning point are stored are scanned once. Shift the line by points,
Furthermore, immediately before the line shift, an area corresponding to the latest scanning point from the first RAM is stored in the area in the second RAM in which a discrete digital value string was stored corresponding to the scanning point immediately before the latest scanning point. a latch gate circuit for temporarily storing a sequence of discrete digital values and for line-shifting the discrete digital values in the second RAM; In order to read out the discrete digital values in the second RAM for each scanning point, which are necessary when reproducing each point on the center line, reproduce the address in the second RAM of the discrete digital value for each scanning point. a third RAM that stores a focus table formed into a table corresponding to target points; and the second RAM.
an adder for adding up a plurality of discrete digital values read from M; a fourth RAM for storing the reproduction results for storing the results added by the adder; sends an address to be accessed from the third RAM to the second RAM, and
a reproduction operation control circuit that instructs the address of the discrete digital value of the second RAM to be line shifted and the address of the first RAM to be latched by the latch gate circuit, and controls the timing of the line shift and reproduction operation; A changeover switch for selecting test mode or flaw detection/inspection mode in a synthesis processing device having
A first ROM for a test mode that transfers data to the first RAM when in the test mode according to a signal from the changeover switch, and a ROM for a test mode that transfers predetermined data to the third RAM when in the test mode. a second ROM, an address switch capable of specifying an address in the fourth RAM for storing playback results, and a readout for reading data in the address of the fourth RAM for storing playback results specified by the address switch; A synthetic aperture processing device comprising: a circuit; and a determination circuit that compares a preset determination value with data in the fourth RAM address for storing reproduction results and outputs a determination result. .