JPH0268584U

JPH0268584U -

Info

Publication number: JPH0268584U
Application number: JP14726588U
Authority: JP
Priority date: 1988-11-11
Filing date: 1988-11-11
Publication date: 1990-05-24

Description

[Brief explanation of the drawing]

第１図は本考案によるＲＧＢ回路の実施例を示
す回路図である。第２図は第１図の動作を説明す
るための波形図である。第３図は従来のＲＧＢ回
路の例を示す回路図である。１，１１……発振回路、２，１２……遅延回路
、３，１３……ラツチ回路、４……抽出回路、１
４……セレクタ回路、１５……可変遅延回路。 FIG. 1 is a circuit diagram showing an embodiment of an RGB circuit according to the present invention. FIG. 2 is a waveform diagram for explaining the operation of FIG. 1. FIG. 3 is a circuit diagram showing an example of a conventional RGB circuit. 1, 11...Oscillation circuit, 2, 12...Delay circuit, 3, 13...Latch circuit, 4...Extraction circuit, 1
4... Selector circuit, 15... Variable delay circuit.

Claims

[Scope of utility model registration request]

an oscillation circuit, and 1 of the output signal period of the oscillation circuit;
/2n is the basic delay amount, and 2n of this basic delay amount
A first delay signal group of n pieces having twice the amount of delay and (2
n-1) a delay circuit that outputs a second delay signal group having n-times the amount of delay; a latch circuit that samples the first delay signal group using a vertical synchronization signal; and n latch circuits. When the levels of m and (m+2) times delayed signals among the output signals of are different,
A delay whose minimum unit of offset amount is twice the basic delay amount, has a function of varying this offset amount, and has a delay amount that is (m+1) times the delay amount of the other delay signal group, plus the offset amount. A clock generation circuit for an RGB circuit consisting of an extraction circuit for extracting signals.