JPS6045513U - Sine wave generation circuit - Google Patents

Sine wave generation circuit

Info

Publication number
JPS6045513U
JPS6045513U JP13784083U JP13784083U JPS6045513U JP S6045513 U JPS6045513 U JP S6045513U JP 13784083 U JP13784083 U JP 13784083U JP 13784083 U JP13784083 U JP 13784083U JP S6045513 U JPS6045513 U JP S6045513U
Authority
JP
Japan
Prior art keywords
sine wave
output
switchers
input
generation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13784083U
Other languages
Japanese (ja)
Inventor
生明 松浦
宮内 直城
Original Assignee
日立電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電子株式会社 filed Critical 日立電子株式会社
Priority to JP13784083U priority Critical patent/JPS6045513U/en
Publication of JPS6045513U publication Critical patent/JPS6045513U/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案のブロック図で、1はカウンタ、2はメ
モリ、3はD/A変換器、4は反転回路、第2図は、本
考案の波形チャートである。
FIG. 1 is a block diagram of the present invention, where 1 is a counter, 2 is a memory, 3 is a D/A converter, 4 is an inverting circuit, and FIG. 2 is a waveform chart of the present invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 水平同期信号をクロック入力とし垂直同期信号をリセッ
ト入力とするカウンタと、該カウンタ出力をアドレス信
号とし対応アドレスに記憶されているサイン波信号の半
周期分の各点のデータを順次読み出すメモリと、該メモ
リ出力をアナログ値に変換するD/A変換器と、該D/
A変換器出力およびこの反転出力をそれぞれ選択切換入
力とする2つの入力選択切換器で構成し、該2つの入力
選択切換器のそれぞれの入力を上記垂直同期信号の周期
で選択切換え出力し、該2つの入力選択切換器より18
0°位相の違うサイン波信号を発生することを特徴とす
るサイン波発生回路。
a counter that uses a horizontal synchronization signal as a clock input and a vertical synchronization signal as a reset input; a memory that uses the counter output as an address signal and sequentially reads out data at each point for a half period of a sine wave signal stored at a corresponding address; a D/A converter that converts the memory output into an analog value;
It is composed of two input selection switchers each having the output of the A converter and its inverted output as selection switching inputs, and selectively switches and outputs the respective inputs of the two input selection switchers at the cycle of the vertical synchronizing signal. 18 from two input selection switchers
A sine wave generation circuit characterized by generating sine wave signals with a 0° phase difference.
JP13784083U 1983-09-07 1983-09-07 Sine wave generation circuit Pending JPS6045513U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13784083U JPS6045513U (en) 1983-09-07 1983-09-07 Sine wave generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13784083U JPS6045513U (en) 1983-09-07 1983-09-07 Sine wave generation circuit

Publications (1)

Publication Number Publication Date
JPS6045513U true JPS6045513U (en) 1985-03-30

Family

ID=30309475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13784083U Pending JPS6045513U (en) 1983-09-07 1983-09-07 Sine wave generation circuit

Country Status (1)

Country Link
JP (1) JPS6045513U (en)

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