JPH0268931A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0268931A JPH0268931A JP22097588A JP22097588A JPH0268931A JP H0268931 A JPH0268931 A JP H0268931A JP 22097588 A JP22097588 A JP 22097588A JP 22097588 A JP22097588 A JP 22097588A JP H0268931 A JPH0268931 A JP H0268931A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- point metal
- high melting
- metal polycide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 238000002844 melting Methods 0.000 claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 45
- 230000008018 melting Effects 0.000 claims abstract description 40
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 13
- 239000002344 surface layer Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 7
- 239000003870 refractory metal Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 235000009508 confectionery Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造工程における高融点金属ポ
リサイドの配線を、半導体基板の主面上に形成する方法
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of forming high melting point metal polycide wiring on the main surface of a semiconductor substrate in the manufacturing process of a semiconductor device.
従来の技術
近年、半導体装置の高速化が進むに従い、高融点金属ポ
リサイドを用いた配線が使用されるようになった。また
、入力回路の保護抵抗など抵抗が必要な箇所がある。2. Description of the Related Art In recent years, as semiconductor devices have become faster and faster, wiring using high-melting point metal polycide has come to be used. Additionally, there are places where resistance is required, such as a protection resistor for the input circuit.
以下に、従来の２種類の膜厚の高融点金属ポリサイドの
配線を同一主面上に形成する方法を第２図（ａ）〜（ｊ
）の工程順断面図に従って説明する。第２図（ａ）に示
すシリコン基板１に、第２図（ｂ）に示すように、酸化
技術等を用いて、第１ゲート絶縁膜２、ＣＶＤ技術等を
用いて、第１多結晶シリコン膜３を形成する。次に、第
２図（Ｃ）に示すように、第１多結晶シリコン膜上に、
第１高融点金属シリサイド膜４を堆積する。次に、第２
図（ｄ）に示すように、第１高融点金属ポリサイドの配
線形成用のフォトレジストマスクパタン１０を形成し、
第２図（ｅ）のように、第１高融点金属シリサイド膜、
第１多結晶シリコン膜、第１ゲート絶縁膜のエツチング
を行う。前記フォトレジストマスクバタン１０を除去し
、第２図げ）に示すように、酸化技術等により第２ゲー
ト絶縁膜１１を形成し、第２図（ｇ）に示すように、Ｃ
ＶＤ技術を用いて第２多結晶シリコン膜１２を形成する
。次に、第２図（Ｗに示すように、第２多結晶シリコン
膜１２上に、第２高融点金属シリサイド膜１３を堆積す
る。次に、第２図（ｉ）に示すように、第２高融点金属
ポリサイドの配線形成用のフォトレジストマスクパタン
１４を形成し、第２高融点金属シリサイド膜、第２多結
晶シリコン膜、第２ゲート絶縁膜のエツチングを行い、
第２図（ｊ）のように、膜厚の違う高融点金属ポリサイ
ドの配線層を形成する。Below, the conventional method of forming high-melting point metal polycide interconnects with two different film thicknesses on the same main surface is shown in Figures 2(a) to (j).
) will be explained according to the step-by-step cross-sectional diagrams. As shown in FIG. 2(b), a first gate insulating film 2 is formed on the silicon substrate 1 shown in FIG. A film 3 is formed. Next, as shown in FIG. 2(C), on the first polycrystalline silicon film,
A first refractory metal silicide film 4 is deposited. Next, the second
As shown in Figure (d), a photoresist mask pattern 10 for forming wiring of the first high melting point metal polycide is formed,
As shown in FIG. 2(e), a first high melting point metal silicide film,
The first polycrystalline silicon film and the first gate insulating film are etched. The photoresist mask button 10 is removed, and a second gate insulating film 11 is formed by oxidation technique as shown in FIG.
A second polycrystalline silicon film 12 is formed using VD technology. Next, as shown in FIG. 2 (W), a second high melting point metal silicide film 13 is deposited on the second polycrystalline silicon film 12.Next, as shown in FIG. 2. Forming a photoresist mask pattern 14 for forming wiring of high melting point metal polycide, etching the second high melting point metal silicide film, second polycrystalline silicon film, and second gate insulating film,
As shown in FIG. 2(j), wiring layers of high melting point metal polycide having different film thicknesses are formed.
発明が解決しようとする課題
従来の技術では、違う膜厚の高融点金属ポリサイドの配
線を別々に形成しなければならず、工程の複雑化及び歩
留りの低下の要因となっていた。Problems to be Solved by the Invention In the conventional technology, interconnects made of high melting point metal polycide having different film thicknesses had to be formed separately, which complicated the process and reduced yield.
本発明の目的は、高融点金属ポリサイドの配線形成工程
において、高融点金属ポリサイド膜を選択的に除去する
ことにより、違う膜厚の高融点金属ポリサイドの配線を
同時に形成することである。An object of the present invention is to simultaneously form high melting point metal polycide interconnects of different thicknesses by selectively removing the high melting point metal polycide film in the high melting point metal polycide interconnect formation process.
課題を解決するための手段
この目的を達成するためには、高融点金属ポリサイド上
にプラズマＣＶＤ法により、シリコン窒化膜を形成する
ことにより、高融点金属ポリサイド膜がシリコン窒化膜
の応力によりはがれる。次に、シリコン窒化膜を除去す
ることにより、はがれた高融点金属ポリサイド膜も除去
される。そこで、高融点金属ポリサイド周辺の一部にシ
リコン酸化膜を形成すると、シリコン窒化膜の応力に影
響を受けないので、同シリコン窒化膜の付着した部分の
高融点金属シリサイド膜の一部がはがれることはなく、
ここで、シリコン窒化膜を除去しても高融点金属ポリサ
イド膜が除去されることはない。このことを利用して、
主面上にシリコン酸化膜成長後、高融点金属ポリサイド
膜を除去したい部分のシリコン酸化膜を選択的にエツチ
ングすることにより、高融点金属ポリサイド膜を選択的
に除去することができる。Means for Solving the Problem In order to achieve this object, a silicon nitride film is formed on a high melting point metal polycide by plasma CVD, so that the high melting point metal polycide film is peeled off due to the stress of the silicon nitride film. Next, by removing the silicon nitride film, the peeled off high melting point metal polycide film is also removed. Therefore, if a silicon oxide film is formed around a part of the high-melting point metal polycide, it will not be affected by the stress of the silicon nitride film, so part of the high-melting point metal silicide film will peel off in the area where the silicon nitride film is attached. Not,
Here, even if the silicon nitride film is removed, the high melting point metal polycide film is not removed. Taking advantage of this,
After the silicon oxide film is grown on the main surface, the high melting point metal polycide film can be selectively removed by selectively etching the silicon oxide film in the portion where the high melting point metal polycide film is to be removed.
作用
本発明によると、違う膜厚の高融点金属ポリサイドの配
線を同時に、選択的に形成することにより、工程の簡略
化ができ、歩留りが向上する。According to the present invention, by simultaneously and selectively forming interconnections of high melting point metal polycide having different film thicknesses, the process can be simplified and the yield can be improved.
実施例
本発明の実施例を第１図（ａ）〜（給の工程順断面図に
従って説明する。第１図（ａ）に示すシリコン基板１に
、第１図（ｂ）に示すように、第１ゲート絶縁膜２を４
０ｎｍ程度、第１多結晶シリコン膜３を３００ｎｍ程度
形成する。次に、第１図（Ｃ）に示すように、第１多結
晶シリコン膜上に、第１高融点金属ポリサイド膜４を２
００ｎｍ程度形成する。Embodiment An embodiment of the present invention will be explained with reference to step-by-step sectional views of FIGS. 1(a) to 1(b).The silicon substrate 1 shown in FIG. The first gate insulating film 2 is
The first polycrystalline silicon film 3 is formed to have a thickness of about 300 nm. Next, as shown in FIG. 1(C), a first high melting point metal polycide film 4 is deposited on the first polycrystalline silicon film.
A thickness of about 00 nm is formed.
次に、第１図（ｄ）に示すように、２種類の膜厚をもつ
高融点金属ポリサイドの配線の形成用マスクパタン５を
形成し、第１高融点金属ポリサイド膜４、第１多結晶シ
リコン膜３．第１ゲート絶縁膜２のエツチングを行い、
第１図（ｅ）に示す構造を得る。次に、第１図（ｆ）に
示すように、高融点金属ポリサイド配線４上に、シリコ
ン酸化膜６を３５０ｎｍ程度形成する。次に、第１図（
ｇ）に示すように、異種膜厚の高融点金属ポリサイド配
線形成用のフォトレジストマスクパタン７を形成し、シ
リコン酸化膜のエツチングを行い、第１図（ｈ）のよう
に、一方の側の高融点金属ポリサイド膜の所定厚さ表面
層を露出させ、２種類の膜厚の高融点金属ポリサイドの
配線部分に分ける。次に、第１図（ｉ）に示すように、
プラズマＣＶＤ法により、シリコン窒化膜８を１μｍ程
度形成する。この段階で、一方の側の高融点金属ポリサ
イド膜は、シリコン酸化膜６から露出された表面層が所
定厚さだけ剥離する。次に、シリコン窒化膜８を、例え
ば１５０℃程度に熱したリン酸に浸し除去すると、第１
図（ｊ）に示すように、違う膜厚の高融点金属ポリサイ
ドの配線９が形成される。次に第１図（ｋ）に示すよう
に、フッ酸水溶液により酸化膜を除去する。Next, as shown in FIG. 1(d), mask patterns 5 for forming interconnections of high melting point metal polycide having two types of film thickness are formed, and the first high melting point metal polycide film 4, the first polycrystalline Silicon film 3. Etching the first gate insulating film 2,
The structure shown in FIG. 1(e) is obtained. Next, as shown in FIG. 1(f), a silicon oxide film 6 of about 350 nm is formed on the high melting point metal polycide wiring 4. Then, as shown in FIG. Next, Figure 1 (
As shown in Fig. 1(h), a photoresist mask pattern 7 for forming high-melting point metal polycide wiring with different film thicknesses is formed, and the silicon oxide film is etched, as shown in Fig. 1(h). The surface layer of the high melting point metal polycide film is exposed to a predetermined thickness and divided into wiring portions of high melting point metal polycide having two different thicknesses. Next, as shown in Figure 1(i),
A silicon nitride film 8 having a thickness of about 1 μm is formed by plasma CVD. At this stage, the surface layer of the high melting point metal polycide film on one side exposed from the silicon oxide film 6 is peeled off by a predetermined thickness. Next, the silicon nitride film 8 is removed by immersing it in phosphoric acid heated to about 150°C, for example.
As shown in Figure (j), interconnections 9 of high melting point metal polycide having different film thicknesses are formed. Next, as shown in FIG. 1(k), the oxide film is removed using a hydrofluoric acid aqueous solution.
発明の効果
本発明によれば、異種の膜厚の高融点金属ポリサイドの
配線を同時に、選択的に形成することにより、工程の簡
略化ができ、歩留りが向上する。Effects of the Invention According to the present invention, by simultaneously and selectively forming interconnections of high melting point metal polycide having different film thicknesses, the process can be simplified and the yield can be improved.
第１図は本発明によって、異種の膜厚の高融点金属ポリ
サイドの配線を形成するときの工程順断面図、第２図は
従来の製造方法で、異種の膜厚の高融点金属ポリサイド
の配線を形成するときの工程順断面図である。
１・・・・・・半導体基板、２・・・・・・第１ゲート
絶縁膜、３・・・・・・第１多結晶シリコン膜、４・・
・・・・第１高融点金属ポリサイド膜、５・・・・・・
フォトレジストマスクバタン、６・・・・・・シリコン
酸化膜、７・・・・・・フォトレジストマスクバタン、
８・・・・・・シリコン窒化膜、９・・・・・・異種の
膜厚の高融点金属ポリサイド膜。
代理人の氏名 弁理士 粟野重孝 ほか１多忙
＋−−−牛導イ本：！＆、オ反
２− 寮ｆゲート絶橘狭
３−ｆ、 １号緒晶ンヮコン膜
４゛−°第１高睨校￥、塵鴎もシソブイ）′ｌｌ菓に・
−シソモノ峻イｌ：、嘆
８− シリボン菫イし膜
へ
芭Fig. 1 is a cross-sectional view of the steps in forming interconnections of high melting point metal polycide with different film thicknesses according to the present invention, and Fig. 2 shows interconnections of high melting point metal polycide with different film thicknesses using the conventional manufacturing method. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First gate insulating film, 3... First polycrystalline silicon film, 4...
...First high melting point metal polycide film, 5...
Photoresist mask bang, 6... Silicon oxide film, 7... Photoresist mask bang,
8...Silicon nitride film, 9...High melting point metal polycide film with different film thicknesses. Name of agent: Patent attorney Shigetaka Awano and 1 other busy people &, Ohan 2- Dormitory F Gate Zetsukanasa 3-f, No. 1 Ogaki Nwakon Membrane 4゛-° 1st High School ￥, Dust Seagull also Shisobui)'ll confectionery.
-Shisomono sharp Il:, lament 8- Siribon violet, and then turn to the membrane
Claims (1)
する工程と、同主面上にシリコン酸化膜を形成する工程
と、前記シリコン酸化膜の一部を除去し、前記高融点金
属ポリサイド膜の所定厚さ表面層を露出する工程と、前
記主面上にシリコン窒化膜を形成する工程と、前記シリ
コン窒化膜を除去して、前記高融点金属ポリサイド膜の
所定厚さ表面層を剥離除去する工程をそなえたことを特
徴とする半導体装置の製造方法。A step of forming a high melting point metal polycide film on the main surface of a semiconductor substrate, a step of forming a silicon oxide film on the main surface, and a step of removing a part of the silicon oxide film and forming the high melting point metal polycide film. a step of exposing a predetermined thickness of the surface layer of the refractory metal polycide film, a step of forming a silicon nitride film on the main surface, and a step of removing the silicon nitride film and peeling off the predetermined thickness of the surface layer of the high melting point metal polycide film. 1. A method for manufacturing a semiconductor device, comprising a step of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22097588A JPH0268931A (en) | 1988-09-02 | 1988-09-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22097588A JPH0268931A (en) | 1988-09-02 | 1988-09-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0268931A true JPH0268931A (en) | 1990-03-08 |
Family
ID=16759501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22097588A Pending JPH0268931A (en) | 1988-09-02 | 1988-09-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0268931A (en) |
-
1988
- 1988-09-02 JP JP22097588A patent/JPH0268931A/en active Pending
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