JPH0270177A - Digital gamma correction circuit - Google Patents

Abstract

PURPOSE:To enable to handle gamma correction data longer than the data length of the correction data of a memory, and to contrive gamma correction which is of high resolution and is good in signal/noise ratio by forming the gamma correction data by adding reference data to input data when the input data is longer than the reference data. CONSTITUTION:A comparator 3 switches output data D3 from a switching circuit 4 into DIN or Dref according to whether the input data DIN is smaller or larger than the reference data Dref respectively. A data table in which the gammacorrection data D1 having the value of difference between the gamma corrected data DOUT and the data D3 from the circuit 4 is written beforehand in an address corresponding to the data DIN is formed in the memory 2, and the gamma corrected data DOUT can be formed by summing the gamma correction data D1 from the memory 2 and the data D3. Accordingly, the gamma correction data longer than the data length of the correction data of the memory can be handled, and the gamma correction which is of the high resolution and is good in the signal/noise ratio of a picture can be realized by a single 8-bit memory.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital γ correction circuit that performs γ correction of a video signal by digital signal processing, and is applied to, for example, an imaging signal processing circuit of a digital video camera device. It is something.

B1 A Summary of the Invention The present invention is a digital γ correction circuit that performs γ correction of a video signal by digital signal processing, which adds output data from a data output means to γ correction data read from a memory in accordance with input data. By forming the T-correction method data using the above-mentioned data, it is possible to handle T-correction method data that is larger than the data length of the data read out from the memory.

C3 Conventional technology Conventionally, input video signals are subjected to predetermined γ correction and then output.
A correction circuit is used, for example, in an imaging signal processing circuit of a video camera device.

Furthermore, with the recent development of digital video camera devices, digital γ correction circuits that perform the above γ correction using digital signal processing have also been put into practical use. This digital γ
The correction circuit has a data table of T correction method data corresponding to the T characteristic formed in the memory, and uses input data indicating the level of the input video signal as the read address data of the memory to read the γ correction method data. It is designed to convert data.

By the way, -S memory is widely used in which the data length of the data to be sold is 1 byte, that is, 8 bits. However, a digital γ correction circuit that uses such a memory alone does not perform the γ correction circuit that uses the memory alone.
Since the data length of the correction method data can only be handled up to 8 bits, sufficient resolution cannot be obtained and the image S
/N also had the disadvantage that it could not be said to be good.

Further, in order to overcome the above-mentioned drawbacks, a digital .gamma. correction circuit as shown in FIG. 3, for example, is known as a digital .gamma. correction circuit capable of handling T correction method data having a data length of 10 bits or more.

That is, this digital γ correction circuit has a memory block 00) connected between input and output terminals, and the memory block 00) includes an upper focus memory (11) and a lower bit memory Q211. Each memory (11), θ2) constituting the memory block 00) has the following:
For example, 10 bits of T-corrected data D is placed at an address corresponding to 10 bits of input data D11+ indicating the level of the input video signal. , is formed by dividing it into the upper 8 bits and the lower 2 bits. In this digital γ correction circuit, input data DIN supplied from the input terminal is used as read address data to read γ-corrected data D from each of the memories (marked 02). , □ are read out, combined into 10-bit data, and output from the output terminal.

D1 Problems to be Solved by the Invention By the way, in the conventional digital γ correction circuit, when the memory is used alone as described above, it is only possible to handle γ correction method data read from the memory with a data length of up to 8 bits. Therefore, there was a drawback that sufficient resolution could not be obtained and the S/N ratio of the image could not be said to be good.

In addition, in order to overcome the above-mentioned drawbacks, the conventional digital γ correction circuit that can handle T-correction method data with a data length of 10 bits or more requires multiple memories (I+), 02) as described above. Met.

However, in this digital γ correction circuit, since the memory block 00) is configured using a plurality of memories C11) and O'l), the mounting area becomes large and
The disadvantages are that the wiring is complicated, the power consumption is high, and the cost is high.

Therefore, the present invention was proposed in view of the above-mentioned actual situation, and it is possible to handle γ correction method data that is larger than the data length of the data read out from the memory, thereby achieving high resolution and reducing the S/N of the image. A new configuration that makes it possible to achieve good γ correction, and also allows the memory to be used independently, making it easier to reduce the mounting area, simplify wiring, reduce power consumption, and lower prices. The purpose of the present invention is to provide a digital γ correction circuit.

E9 Means for Solving Problems In order to achieve the above-mentioned object, the digital γ correction circuit according to the present invention includes a memory to which input data indicating the level of an input video signal is supplied as read address data of the γ correction data. , a comparison means for comparing the input data with predetermined reference data; and according to the output of the comparison means, when the input data is smaller than the reference data, the input data is set as output data; data output means for outputting the reference data when the data is larger than the reference data, and adding the γ correction data from the memory and the output data from the data output means to form and output γ correction method data. Adding means and Oj
:J, the above memory has the above γ according to the above input data.
A data table of γ correction data having a difference value between the correction method data and the output data from the data output means is formed.

F1 action In the digital γ correction circuit according to the present invention, when input data indicating the level of an input video signal is supplied, γ correction data corresponding to the input data is read out from the memory and outputted, and reference data is also read out. The reference data or the input data is output as output data from the data output means by controlling the comparison means according to the magnitude of the input data, and these γ correction data and the output data of the data output means are added. T-correction method data is formed. A data table of γ correction data whose data length is shorter than that of the γ correction method data is formed in the memory.

G. Examples Hereinafter, examples to which the present invention is applied will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of the digital γ correction circuit (1) of this embodiment.

In this FIG. 1, the digital γ correction circuit (1)
includes a memory (2), a comparison circuit (3) used as a comparison means, and a switching circuit (4) used as a data output means.
) and an addition circuit (5) used as addition means.

The input terminal (IN) has a 1 signal indicating the level of the input video signal.
0-bit input data DIN is supplied. This input data DIN is stored in the memory (2) and the comparison circuit (3).
and the switching circuit (4). Further, reference data Drat having a predetermined value (for example, a value corresponding to a 100% level) is supplied to the input terminal (REF). This reference data Dre
f is supplied to the comparison circuit (3) and the switching circuit (4), respectively.

Furthermore, the output end of the comparison circuit (3) is connected to the switching circuit (4). The output end of the memory (2) and the output end of the switching circuit (4) are connected to the adder circuit (
5) is connected to the output terminal (OIIT).

The operation of this embodiment having such a configuration will be explained with reference to FIG. 2. In FIG. 2, the horizontal axis shows the value of the input data DIN supplied to the input terminal (IN), and the vertical axis shows the corresponding T-corrected data output from the output terminal (OUT). D. , indicates the value of T.

First, the comparison circuit (3) compares the input data DI8 supplied from the input terminal (IN) and the input terminal (REF).
) and the switching circuit (4) is controlled as follows depending on the magnitude of the data.

That is, the comparison circuit (3) receives the input data DI
When data from the data Do indicating the 0 level of the input video signal to the reference data Dr and f is supplied as N, the input data DIN is the reference data D.
Comparison data D2 indicating that it is smaller than raf is supplied to the switching circuit (4). As a result, the above switching circuit (
4) outputs input data DIR from the input terminal (IN) as output data D, as shown by straight line A in FIG.

Furthermore, when data larger than the reference data D1° is supplied as the input data DIN, the comparison circuit (3) outputs comparison data D indicating that the input data DIN is larger than the reference data DrllF.
2 is supplied to the switching circuit (4). As a result, the switching circuit (4), as shown by straight line B in FIG.
The reference data D rsf from the input terminal (REF) is output as output data D.

Next, in the memory (3), the γ correction method data D is stored at the address corresponding to the input data DIN, as indicated by diagonal lines in FIG. T correction data D having a value of the difference between LIT and the output data D3 from the switching circuit (4);
A data table has been created in which the data has been written.

That is, this memory (2) stores, for example, input data DA shown in FIG. 2 at addresses corresponding to input data D8 from the data D0 to the reference data Dr, f.
γ correction data D for the above T correction method data D. uy and the above output data D.

That is, T correction data D1 having a difference value from the input data DIN is written.

The memory (2) also contains the reference data Dr,
To the address corresponding to the input data DIN larger than t,
For example, the input data D! shown in FIG. The above T correction method data D, such as T correction data D for l. LIT and the above output data D3, that is, the above %'<% data D
T correction data D having a value of difference from 1@f is written.

Further, in this embodiment, a predetermined white level D wcL and the above-mentioned standard are set at the address corresponding to the input data DIH larger than the predetermined input data Dc in the memory (2), as indicated by DC in FIG. Fixed T correction data D1 having a difference value from data D ref is written.

Accordingly, in this embodiment, when input data DIN larger than the predetermined input data DC is supplied to the input terminal (IN), the T correction l simultaneous data D is supplied. 0. are all at the above white level D wct , and a so-called white clip is performed.

The T correction data D written in these memories (2) are
By appropriately setting the reference data Drel, the data length of one word does not exceed one byte, which is 8 bits. Therefore, the memory (2
) is a general one where the data length of one word is 8 bits1
It can be composed of pieces.

The T correction data D read from the memory (2) is
The adding circuit (5) adds the output data D3 of the switching circuit (4) to the T-corrected data D. , T, and are output from the output terminal (OUT).

In this way, the digital γ correction circuit (1) of this embodiment adds the γ correction data D from the memory (2) and the output data D3 of the switching circuit (4) to obtain the γ correction method data. D. , by forming T.
γ read from the data table in memory (2) above
The γ correction method data D has a data length larger than the data length (8 bits) of the correction data D1. Ur (10 bits)
can be handled. Therefore, the first digital γ correction circuit (1) processes γ-corrected data D up to the data length of the data read from the memory. Compared to conventional digital gamma correction circuits that can only handle images, gamma correction with high resolution and good image S/N ratio can be achieved.

Moreover, in the digital γ correction circuit (1) of this embodiment,
The memory (2) can be constituted by one general memory whose data length of one word is 8 bits.

Therefore, in the digital γ correction circuit (1), compared to the conventional digital γ correction circuit configured using a plurality of memories, the mounting area can be reduced, wiring can be simplified, and , it is also possible to realize reductions in power consumption and prices.

Note that the above T of the digital γ correction circuit to which the present invention is applied
Correction method data D. Of course, the rate of change in IIT, etc. may be other than that shown in FIG. 2 above. Further, in the digital Tl11i positive circuit according to the present invention, the rate of change in the γ correction method data D0Llf can be easily determined by changing the T correction data D1 written in the data file of the memory (2). and can be changed arbitrarily.

H6 Effects of the Invention In the digital γ correction circuit according to the present invention, when input data indicating the level of an input video signal is supplied, a γ correction value corresponding to the input data is outputted from the memory, and a γ correction value corresponding to the reference data is output. The reference data or the input data is output as output data from the data output means by controlling the comparison means according to the magnitude of the input data, and these γ correction data and the output data of the output means are added to perform r correction. Legal data is formed.

Therefore, in the digital γ correction circuit according to the present invention,
It is possible to handle r-correction method data that is larger than the data length of the data read from the data table in the memory. Therefore, compared to the conventional digital γ correction circuit, which can only handle T-correction data up to the data length of the data read out from memory, the digital γ correction circuit has higher resolution and better image S/N. Correction can be achieved.

Furthermore, the digital gamma correction circuit according to the present invention can be configured with one memory.

Therefore, in the digital T correction circuit described in item 1, compared to the conventional digital γ correction circuit configured using a plurality of memories, the mounting area can be reduced, wiring can be simplified, and moreover, It is also possible to reduce power consumption and lower prices.

■...Digital γ correction circuit 2...Memory 3... Comparison circuit 4...Switching circuit used as data output means 5... Addition circuit

Claims (1)

[Scope of Claims] A memory to which input data indicating the level of an input video signal is supplied as read address data of γ correction data, a comparing means for comparing the input data with predetermined reference data, and a comparing means for comparing the input data with predetermined reference data. a data output means for outputting the input data as output data when the input data is smaller than the reference data and using the reference data as output data when the input data is larger than the reference data; and an addition means for adding the γ-corrected data from the input data and the output data from the data output means to form and output γ-corrected data, and the memory stores the γ-corrected data according to the input data. and the output data from the data output means.