JPH02707B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to high-speed switching of screens. For example, a system in which a display, an input device, etc. are controlled by a microcomputer is disclosed in Japanese Patent Laid-Open No. 125732/1983.
(First country filing date, April 6, 1977) Characters and symbols to be displayed on the CRT (cathode tube) surface,
Adding colors to graphs and the like is commonly done in conventional character displays and graphic displays. In such conventional systems, only static images such as characters need to be displayed, and a color code bit is added to a part of the display code stored in the refresh memory (memory that stores one screen worth of images to be displayed on a CRT). , which also performs color display.

By the way, in the general display system as mentioned above, for example, in a system such as a video game that displays still images (for example, the court and net in a tennis game) and moving images (for example, the ball and racket in a tennis game) at the same time, the color There is a problem with the specified method. That is, in the conventional display system, n
(dot) xm (dot) The color was specified for each pixel (a section representing a character or symbol), and the color was only specified for the characters and symbols to be displayed, so both still images and videos were used. It was difficult to specify arbitrary colors for the background and pictures.

Furthermore, it is extremely difficult to rewrite the refresh memory in response to rapidly changing images such as moving images.

One object of the present invention is to reduce the burden on the image control circuit during high-speed refresh.

One object of the present invention is to provide a video display system capable of high-speed screen switching.

The present invention will be specifically described below using examples and with reference to the drawings.

FIG. 1 is a block diagram showing a video display system according to an embodiment of the present invention.

As shown in the figure, ROM (read only memory)
1. RAM (random access memory) 2, central processing unit (CPU) 3 with 4 input/output ports (I/Oport) address bus AB, data bus DB with serial/parallel converter (P/S) 5, color A code register (CR) 6 is connected. The display data serially converted by the serial/parallel converter 5 is stored in refresh memories (RM ₁ , RM ₂ , RM ₂ ') 7 to 9.
given to. These refresh memories 7
Address control of 9 to 9 is performed by a color controller (CLC) 10. That is,
The color controller 10 performs address control when display data is written to the refresh memories 7 to 9 by the CPU 3, and address control when display data written to the refresh memories 7 to 9 is displayed on the television. Let's do it. The address information of refresh memories 7 to 9 to which display data should be written is stored in the CPU 3.
When the display data is output from the refresh memory 7 to 9 to the address bus AB, the color controller 10 forms address information in which the display data is to be written in the refresh memories 7 to 9 in accordance with the address information at that time. As a result, the display data supplied from the CPU 3 to the data bus DB is written into the addresses of the refresh memories 7 to 9 specified by the CPU 3. In this embodiment, as described above, the so-called parallel display data supplied via the data bus DB is converted into serial display data by the serial/parallel converter 5, and the serial display data is converted into serial display data. The data is written into refresh memories 7-9. Therefore, the color controller 10 uses the refresh memories 7 to 9 for one address information supplied from the CPU 3.
is configured to form a plurality of consecutive address information for. The configuration for forming a plurality of consecutive address information from one address information is not shown in the figure because it is neither special nor complicated in itself, but for example, it can receive input address information as preset data and It may consist of counter means for counting clock pulses.

Address control for displaying display data includes a color controller 1 that counts clock pulses for display and thereby forms a count signal as address information that changes sequentially.
This can be done by a counting means (not shown) within 0. Here, the refresh memory (RM ₁ ) 7 is dedicated to still images, and the other refresh memories (RM ₁ , RM ₂ ') 8 and 9 are memories dedicated to moving images. The reason why there are two memories (RM ₂ and RM ₂ ') dedicated to video is that the CPU
This is because it is necessary to perform interlacing in order to secure the processing time of 3. That is, the color controller 10 alternately writes and reads display data into and from the two refresh memories 8 and 9 dedicated to moving images for each display frame, as will become clear from the description below. 1 like this
The alternating access of the two memories 8 and 9 for each display frame can be controlled by display frame indicating means (not shown) in the color controller 10, such as a flip-flop whose state is reversed for each display frame. As mentioned above, the color controller 10 has refresh memory 7 to
In addition to controlling the address of color code register (CR) 6, it also reads the color code in color code register (CR) 6 and sends it to the R (red), B (blue), and G (green) signals that are the output patterns from refresh memories 7 to 9. It also has the function of switching. The configuration of the color controller 10 that performs the switching function to R, B, and G signals can be configured in the same manner as the prior art described above, that is, the technique of adding color code bits to each display code. In other words, the R, B, and G signals for moving images are refreshed.
It can be formed by a logic circuit or a decoder such as an AND circuit that receives display data signals read out alternately from the memories 8 and 9 and a color code for a moving image supplied from the color code register 6. Note that 11 indicates a CRT.

The ROM 1 contains programs for playing games, tables for code/pattern conversion, and the like. The game is executed by executing the program stored in ROM1. RAM2 is used as a work memory when CPU3 executes a game program. The input/output port 4 receives external input necessary for the progress of the game, such as the direction of movement of the racket and its position information in the case of a tennis game, by the player. This information is (X ₁ , Y ₁ ) (X ₂ , Y ₂ ) for CPU3.
Entered as coordinates.

In addition, in the above example, the refresh memory for still images and moving images is provided separately as described above, and the color code register 6 is specified in advance to specify the color of each part according to the content of the game. That is. For example, in a tennis game, an 8-bit register is used, the first 2 bits are green (court color), the middle 3 bits are white (line and net colors), and the last 3 bits are green (court color).
Specify yellow (the color of the racket and ball) for the bit as shown in Figure 3. Color specification can be done in the same way as color specification in the prior art. For example, in a 2-bit color code, if 1 bit of the 2 bits is used to indicate red and the remaining 1 bit is used to indicate green, the red indicator bit for green is ``0''. This can be specified by setting the green indicator bit to a non-indicating level such as "1" and setting the green indicator bit to an indicator level such as "1". Similarly, 3
In the bit color code, white can be specified by setting all of the red indicator bit, blue indicator bit, and green indicator bit to an indicator level such as "1", and yellow can be specified by setting the red indicator bit and the green indicator bit to an indicator level such as "1". This can be specified by setting the green indicator bit to the indicator level.

The operation of the embodiment of the present invention having the above configuration will be explained as follows.

Now, assuming a tennis game, when the game starts, the CPU 3 creates color codes for still images and videos as color registers or still image information, and creates tennis courts, nets, scoreboards, etc. from the fixed game data in ROM ₁ . Transfer to refresh memory (RM ₁ ) 7. Subsequently, the positions of the two rackets and the ball are set to initial values and transferred to the refresh memory (RM ₂ ) 8 as a moving image.

After that, by receiving a start signal from outside,
The game program starts, and the player moves the racket in accordance with the ball using a joystick or the like. As shown in Figure 2, this racket position information is taken into the CPU 3 in units of vertical synchronization signals from the TV, that is, frames (1 frame time 33.33 msec), and the relative position to the ball coordinates is calculated by the CPU 3. A series of calculations are performed to determine whether the ball is a hit or a hit, and if it is a hit, the coordinates of the ball are changed, and the results are transferred to the refresh memory ( _RM2 ') 9 as new moving image information. That is,
In this embodiment, as shown in FIG. 2, in the first frame time (33.33 msec), a still image is displayed by the refresh memory (RM ₁ ) 7, and a still image is displayed by the refresh memory (RM ₂ ') 9. A moving image (for example, a ball, etc.) is displayed, and the CPU 3 causes the CPU 3 to rewrite the pole position coordinates in the other moving image refresh memory ( _RM2 ) 8.
During the next frame time, the refresh memory (RM ₁ ) 7 displays a still image, and the refresh memory (RM 2 ) 8 displays a new video, and at this stage, the refresh memory (RM ₂ ) 8 displays a new video. The refresh memory ( _RM2 ') 9 is allowed to be rewritten. Therefore, by providing the two video refresh memories RM ₂ and RM ₂ ', it is possible to provide sufficient margin for the processing time of the CPU 3.

Refresh memory 8 or 9 (RM ₂ or
The serial data read from the _RM2 ') becomes the video signal for the television, but when displaying in color, this data cannot be directly modulated and input to the television. However, in the above embodiment, the color code register 6 is prespecified with a code as shown in FIG. 3, and this color code is stored in the color controller 1.
By entering 0 and acting on each bit of the display data read out from the refresh memories 7-9, three hue signals (R, G, B) can be output. In this case, the hue signals (R, G, B) to be supplied to the television are basically a display data signal read out from the refresh memory 7 for still images and a static image signal supplied from the color code register 6. Hue signals (R, G, B) for still images obtained from the color code for images, display data signals read from the refresh memory 7 or 8 for moving images, and color code signals for moving images from the color code register 6. It is obtained by combining the moving image hue signals (R, G, B) obtained by the color code.

Here, in the case of a game like a tennis game,
The lines and net of a tennis court need to be displayed with priority over the display of the court, and the racket and ball need to be displayed with priority over the display of the court, lines and net. Therefore, when the display data from the refresh memory 7 for still images is set to a level such as "1" that should display lines and nets, the color controller 10 selects one of the two color codes for still images. A hue signal (R, G, B) for a still image is formed according to a color code for specifying line and net colors, and conversely, it is confirmed that such display data is not a line or net such as "0". When the signal level is set to the level shown, hue signals (R, G, B) for still images are generated in accordance with the color code for specifying the coat color among the color codes for still images. At the same time, the color controller 10
When the display data from the video refresh memory 8 or 9 is set to a level such as "1" for racket and ball display, the video hue signal (R, G ,B)
form. At this time, in order to satisfy the display priority relationship described above, the hue signal for still images is
For example, the display data for such a moving image may prohibit its occurrence. When the display data from the refresh memory 8 or 9 is set to a level such as "0", a hue signal for a moving image is not generated according to the display data at that time, and instead a hue signal for a still image is generated. A hue signal is generated.

In addition, when actually connecting to a TV, R,
From the G and B hue signals, three signals, a luminance signal Y, color difference signals R-Y, and B-Y, are generated in accordance with the NTSC standard system, and each signal is modulated with a carrier wave.

According to the video display method described above, the refresh memory is provided separately for still images and moving images, and the display color is specified independently for still images and moving images, so it is possible to This greatly simplifies colorization of a system that simultaneously displays moving images.

The present invention is not limited to the above embodiments, and various modifications can be made.

The above embodiment shows the case where only one color code register is used, but if more colors are required, colors can be specified by providing two or more color code registers and switching them as appropriate. good.

The present invention can be used in general video systems, and is particularly effective in video systems, video teaching, and other home video systems in general.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a video display system according to an embodiment of the present invention, FIG. 2 is a timing chart thereof, and FIG. 3 is a diagram for explaining color specification of a color code register. 1...ROM, 2...RAM, 3...CPU, 4
...I/O port, 5...Serial-to-parallel converter, 6...
Color register, 7 to 9... Refresh memory, 10... Color controller, 11...
CRT.

Claims (1)

[Scope of Claims] 1. A plurality of refresh memories each storing image data, and a color code signal for an image data signal that is made independent of the plurality of refresh memories and read from the plurality of refresh memories. an image control circuit for specifying a color for each of the image data from the plurality of refresh memories using the color code signal of the register and for synthesizing the image data so that they are displayed in a composite manner on a single display screen; A video display method characterized by: 2. The video display system according to claim 1, wherein the register comprises a register coupled to the central processing unit via a bus. 3. The video display system according to claim 1 or 2, wherein the register is comprised of a plurality of registers that are used selectively.