JPH027151A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To decrease the burden of a process and to increase bus using efficiency by setting the arbitrating means of an independent bus using right at every processor. CONSTITUTION:Plural sub-stations 8 are connected through common buses B1, B2 and L1 to a common memory 11. The common buses are arbitrated by a main arbitrating circuit 10 and independent sub-arbitrating circuits 14 in the sub-stations. The sub-arbitrating circuit 14 obtains the bus by a bus request L10 from a corresponding processor 13, an ID address B3 from the main arbitrating circuit 10 and the instruction of bus using permission L2. Further, the processor, which uses the bus even after a continuously usable time, is regarded as abnormal, the ID address B3 and resetting L4 are sent to the sub-arbitrating circuit 14, the processor 13 is reset, and the operation of the whole system is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multiprocessor system of a type in which a plurality of processors share a common memory.

(Prior Art) In this type of multiprocessor system, a plurality of processors are connected to a common memory via a bus, and a storage area is usually allocated to each processor in advance. A problem in this type of multiprocessor system is competition for bus use among multiple processors, and it is necessary to arbitrate this bus contention.

As bus arbitration methods, ■polling method, ■contention method, ■token method, etc. have been proposed.

Over 1,000 days (problem to be solved by the invention) However, each of the above arbitration methods has the following drawbacks. First, in the polling method, one of the multiple processors is designated as the main processor, and the remaining processors are designated as sub processors, and the main processor sequentially calls the sub processors to arbitrate the bus between the sub processors, so the number of sub processors increases. As the number of buses increases, a heavy load for bus arbitration is placed on the main processor.

Next, to put it simply, the contention method is a method that allows each processor to randomly access a common memory, and therefore the procedure for avoiding bus contention is extremely complicated.

Furthermore, the token method is a method in which a plurality of processors are sequentially connected to form a ring, and the right to use the bus is given and received by circulating token signals on the ring. In this method, when an abnormality occurs in a processor, the abnormal processor must be disconnected from the system, and in the past, special means for disconnecting the abnormal processor from the system was prepared for each processor.

In view of the above-mentioned drawbacks, the main technical object of the present invention is to provide a multiprocessor system that can reduce the burden on processors regarding bus arbitration by making bus use right arbitration means independent of the processor. It is in.

Another technical problem of the present invention is to configure the arbitration means by installing an arbitration circuit for each processor, so that each arbitration circuit can avoid invalid bus requests from the corresponding processor, thereby improving bus usage efficiency. The aim is to improve.

A further object of the present invention is to improve the reliability of the system by allowing the arbitration circuit to disconnect the abnormal processor from the system when an abnormality occurs in a certain processor.

(Means for Solving the Problems) The present invention provides a multiprocessor system comprising a plurality of processors and having a common memory to which a storage area is allocated in advance to each processor. A part of the bus is a shared bus for the common memory, and an arbitration circuit for the shared bus is provided, and the arbitration circuit includes a main arbitration circuit and a plurality of slave arbitration circuits provided for each processor and connected to the main arbitration circuit. The Bodhi arbitration circuit has a function of performing a bus acquisition operation in response to a bus acquisition request from a corresponding processor and an instruction from the main arbitration circuit, and a function of executing a bus acquisition operation in response to a bus acquisition request from a corresponding processor and an instruction from the main arbitration circuit. It is characterized by having a function of disconnecting from the system, and a function of monitoring the storage area of the common memory allocated to the corresponding processor and notifying the corresponding processor of the arrival of data.

(Function) According to the present invention, since a common memory is interposed between a plurality of processors, data transfer between processors with different processing abilities is prevented from being impaired by the processing ability of a higher-level processor by a lower-level processor. It can be done without.

Furthermore, since each slave arbitration circuit operates independently from its corresponding processor under instructions from the main arbitration circuit, the burden of bus arbitration on each processor is reduced. Furthermore, since each slave arbitration circuit notifies the corresponding processor of the state of data on the bus as event information, invalid bus requests from each processor are avoided and immediacy of system response is maintained. On the other hand, the main arbitration circuit cooperates with each slave arbitration circuit to monitor the presence or absence of an abnormality in each processor, and when an error occurs, the corresponding slave arbitration circuit disconnects the abnormal processor from the system.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and here shows the configuration and connections of a main arbitration circuit 10, a common memory 11, and a slave station 12 of a plurality of slave stations, which are the main parts of the present invention. The slave station 12 includes a processor 13, a slave arbitration circuit 14, and a bus gate circuit 15. The processor 13 connects the common memory 1 to the data bus Bl, address bus B2, and memory control line L1 via the bus gate circuit 15.
1 is connected. The slave arbitration circuit 14 is connected to the main arbitration circuit 1° by an ID address bus B3, a bus permission line L2, a bus request line L3, and a reset line L4. The slave arbitration circuit 14 is also connected to the corresponding processor 13 by a bus request line L10, a bus acquisition notification line L11, a data arrival notification line L12, and a reset line L13. The processor 13 and the slave arbitration circuit 14 have an ID address of 0 or more assigned through an encoding means (not shown), and the connections are the same for the remaining slave stations. In this way, a bus arbitration circuit is constituted by the main arbitration circuit 10 and a plurality of slave arbitration circuits each directly interfaced with a plurality of processors.

Note that, as is well known, each of the plurality of processors is allocated a usage area in the common memory 11 in advance. Therefore, for example, regarding processor 13,
Of course, the processor 13 can write and read data,
When writing and reading data related to the processor 13 by the processors in the memory, only the storage area allocated to the processor 13 is used. Furthermore, the multiprocessor system in this embodiment is composed of a main processor (not shown) that is the center of the system and a plurality of processors corresponding to slave arbitration circuits, but the connection relationship between these is the same as in the conventional system. , illustrations and explanations will be omitted.

Next, the features of the present invention (1) bus arbitration operation, (2) disconnection operation of an abnormal processor, and (2) immediate notification operation upon arrival of data will be explained.

(2) Bus arbitration operation Regarding the slave station 12, the processor 13 issues a bus acquisition request to the corresponding slave arbitration circuit 14 through the bus request line LIO. The main arbitration circuit 1o places the ID address of the slave station (for example, slave station 12) to be permitted to acquire the bus on the ID address bus B3, and then the bus use permission line L
Activate 2.

In slave station 12, slave arbitration circuit F/? ID assigned r14
The address and the ID address on the ID address bus B3 are compared. When the two ID addresses match and a bus acquisition request is received from the processor 13 via the bus request line LIO, the slave arbitration circuit 14 outputs the bus request line L3 in response to the bus use permission signal from the main arbitration circuit 10. At the same time, it notifies the processor 13 of the bus acquisition through the bus acquisition notification line Lll. Incidentally, even if the two ID addresses match, the slave arbitration circuit 14 outputs the bus request line L if there is no bus acquisition request from the processor 13.
3 remains inactive and does not notify the processor 13 of anything.

The processor 13 that has been notified of the bus acquisition accesses the common memory 11. On the other hand, the main arbitration circuit 10
While the bus request line L3 is in the active state, a bus monitoring state is entered to hold the ID address on the ID address bus B3. When access to the common memory 11 is completed in the processor 13 and the bus acquisition request from the processor 13 is released, that is, the bus request line LIO is made inactive, the slave arbitration circuit 14 makes the bus request line L3 inactive and becomes the main The arbitration circuit 1o is notified of the end of bus use.

The main arbitration circuit 10, which was in the bus monitoring state,
3 becomes inactive, the ID address on the ID address bus B3 is updated and permission to use the bus is given to the next slave station. Thereafter, bus arbitration is similarly performed for the processors of all slave stations by the main arbitration circuit 10 and a plurality of slave arbitration circuits.

Then, the slave arbitration circuit checks whether the ID address from the main arbitration circuit matches the granted ID address and responds to the bus acquisition request from the corresponding processor, thereby avoiding invalid bus requests from the processor. Ru.

■ Isolation operation of abnormal processor After the main arbitration circuit 10 enters the bus monitoring state, if the bus request line L3 does not become inactive within the continuous usable time of the bus predetermined in the system, the main arbitration circuit 10 Activate reset line L4. Of course, at this time, the ID address of the processor using the bus is on the ID address bus B3.4 A slave arbitration circuit whose ID address on the ID address bus B3J- matches the assigned ID address is , when the reset line L4 becomes active, the bus request line L3 is made inactive to relinquish the right to use the bus, and the corresponding processor is reset through the reset line 113, no matter what state the corresponding processor is in.

By providing the slave arbitration circuit with the function of disconnecting the abnormal processor in this way, it is possible to prevent the abnormal processor from stopping the shift of the bus usage right and stopping the operation of the entire system.

(2) Immediate Notification Operation When Data Arrives As mentioned above, the storage area of the common memory 11 is allocated in advance for each processor.

Regarding the slave station 12 again, the slave arbitration circuit 14 constantly monitors the allocated storage area in the common memory 11 by monitoring the write permission signal through the memory controller 1 for the write permission signal and read permission signal through the roll line L1. .

When it is detected that another processor has performed a write operation on the allocated storage area, it notifies the processor 13 of data arrival through the data arrival notification line L12 and prompts the processor 13 to read the data. In this way, the immediacy of system response can be maintained.

(Effects of the Invention) As explained above, according to the present invention, data is transferred between multiple processors via a common memory, and
It is possible to provide a multi-ten processor system in which the processing ability of a higher-order processor is not inhibited by a lower-order processor even if the processing abilities of the processors are different. Also,
By making the bus arbitration circuit independent from the processor, the burden on the processor regarding bus arbitration can be reduced. In addition, by notifying the corresponding processor of the bus status from the slave arbitration circuit, it is possible to avoid invalid bus acquisition requests from the processor, increasing bus usage efficiency, and maintaining immediacy of system response. can. Furthermore, by providing the slave arbitration circuit with not only an arbitration function but also a function to isolate the corresponding processor, it is possible to avoid stopping the operation of the entire system in the event of an abnormal processor, thereby improving system reliability. be able to.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the connections and configuration of essential parts of an embodiment of the present invention. In the figure, Ll is a memory control line, B2 is a bus permission line, B3 is a bus request line, B4 is a reset line, B1 is a data bus, B2 is an address bus, B3 is an I) address bus, LIO is a bus request line, Lll is the bus acquisition notification line, L
12 is a data arrival notification line, and Ll3 is a reset line.

Claims (1)

[Claims] 1. In a multiprocessor system consisting of a plurality of processors and having a common memory to which a storage area is allocated in advance to each processor, a part of each bus of the plurality of processors is used as a shared bus for the common memory. and an arbitration circuit for the shared bus, the arbitration circuit consisting of a main arbitration circuit and a plurality of slave arbitration circuits provided for each processor and connected to the main arbitration circuit, each slave arbitration circuit comprising: , a function to perform a bus acquisition operation in response to a bus acquisition request from a corresponding processor and an instruction from the main arbitration circuit; a function to disconnect the corresponding processor from the system according to an instruction from the main arbitration circuit; A multiprocessor system characterized by having a function of monitoring a storage area of the common memory allocated to the processor and notifying the corresponding processor of the arrival of data.