JPH0271602A - oscillation circuit - Google Patents

Abstract

PURPOSE:To obtain an oscillation circuit suitable for integration and with a few amount of oscillation noise by preventing the Q of the oscillation circuit from lowering by reducing influence on the oscillation circuit by using a FET for oscillation and a FET for buffer amplification whose drain or source is connected commonly. CONSTITUTION:A first FET 1 and a second FET 2 are gate-grounded and also, their sources are connected commonly and connected to the drain of a constant current source FET 15. A bias resistor 17 is connected between the drain of the FET 2 and a power source Vcc. The source current also changes according to the change of the source current of the FET 1 by applying an oscillation operation, then, an oscillation signal can be taken out from the drain. The gate width of the FET 2 is around 1/10 that of the FET 1, and the drain current is set at around 1/10 that of the FET 1, which reduces the influence given on the source of FET 1. Also, since no FET is attached in parallel with the drain to which an oscillator 3 is connected, the Q of the oscillation circuit can be prevented from lowering, which further reduces the noise in the oscillation circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an oscillation circuit using FETs, and particularly to a voltage-controlled variable oscillation circuit in which the oscillation frequency is varied.

[Conventional technology]

An example of an integrated voltage-controlled variable oscillator circuit is described in Japanese Patent Application Laid-Open No. 157104/1983, in which a differential amplifier constructed of bipolar transistors is used to construct an oscillator. It is difficult for an integrated circuit oscillator using these bipolar transistors to operate at an oscillation frequency above UHFHF.

In contrast, FET% especially gallium arsenide (GaAs)
The GaAsFET (hereinafter abbreviated as GaAsFET) can operate up to the microwave band, and is disclosed in Japanese Patent Application Laid-Open No. 61-90502.
As seen in the newsletter, a differential oscillator is configured,
[Problem to be solved by the invention] In an oscillator using a GaAs FET, the oscillation noise is St
Larger than (silicon) bipolar transistors, etc.
In the above conventional technology, a dielectric resonator is used and the Q of the external resonant circuit is
The aim is to increase the oscillation noise and reduce oscillation noise.

However, in a voltage-controlled variable oscillation circuit that uses a variable capacitance diode or the like to change the oscillation frequency, there is a problem in that the Q of the variable resonant circuit that determines the oscillation frequency decreases, resulting in increased oscillation noise.

SUMMARY OF THE INVENTION An object of the present invention is to provide a voltage-controlled variable oscillation circuit that uses FETs, is easy to integrate, and has low oscillation noise.

[Means to solve the problem]

In the present invention, a grounded gate type FET oscillator is used in which the gate terminals of the first FET are directly grounded to the ground potential, and the second and first FETs whose drains or sources are commonly connected to the oscillation FET are used. FET as the first FE
The second FET is connected in parallel with T, and the oscillation output is taken out from the source or drain terminal of the second FET.

[Effect]

By grounding the first FET for oscillation to the earth potential, the present invention reduces low frequency noise that causes oscillation noise induced in the gates of the first FET, and
A second FET is connected in parallel with the first FET to obtain an oscillation signal from the second FET to reduce the influence on the resonant circuit that determines the N oscillation frequency, and to reduce the Q of the resonant circuit. By preventing the drop, an oscillation signal with less oscillation noise can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, 1 is a first FET for oscillation, 2 is a second and first FET for taking out the oscillation signal, 30°51 is a differential amplification FET for amplifying the oscillation signal, 32 is a constant current source FET,
5 is an oscillation resonator with a coupling capacitor 8 and a resonant coil 11
, a variable capacitance diode 9, and a capacitor 10 for capacitance variable range correction, and is connected to the drain terminals of the first and first FETs 1. 6.7 is the first FE
In the T feedback capacitor, the gate terminal (G) of the first FET 1 is connected to the ground potential, and the source (S)
is grounded through resistor 5. The second grounded gate,
The drain (D) of the first FET 2 is connected to the drain of the first FET 1, and the source is connected to the ground via a resistor 16.

The oscillation signal is taken out from the second and first FETs 20 and applied to the gate of the FET 50 via a resistor 56. Resistors 65 to 57 are bias resistors, and the gate of FET 31 is short-circuited at high frequency with a capacitor 58.
The unbalanced signal input to 50 is converted into a balanced signal.

39 and 40 are balanced output terminals for the oscillation signal, which are led to a mixer inside the integrated circuit, which will be explained separately. A portion surrounded by a dashed line 50 represents an integrated circuit portion, and 51 to 55 are terminals for connecting to an external circuit. Further, 13 is a high frequency choke coil, and 60 is an oscillation power supply terminal, which supplies bias to the first FET 1. Reference numeral 61 denotes an oscillation frequency control voltage terminal which applies a voltage to the variable capacitance diode 10 through the bias resistor 12 to vary the capacitance, thereby controlling the oscillation frequency.

In FIG. 1, a feedback capacitor 6.7 is connected between the drain and source of the first FET 1 to perform a Clap-type oscillation, and the first FET 1 and the first FET 1 The drains of the second FETs 2 are connected in common and connected in parallel to divide the oscillation signal. 2nd, 1st F
The gate width of ET2 is 1 compared to the first and first FET2.
/10@A degrees, and the drain current is 1
/10, and the impedance on the drain side of the second and first FETs 2 as seen from the first and first FETs 1 is high, reducing the influence on the resonant circuit 6, and reducing the Q of the resonant circuit. In this state, an oscillation signal can be taken out, and the first FET 1 performs an oscillation operation on the gate ground plane, which reduces low frequency noise induced in the gate, converted into an excavation signal, superimposed, and becomes oscillation noise. Therefore, a voltage-controlled variable oscillation circuit using FETs with less oscillation noise can be obtained. In addition, in this embodiment, since the gate and drain terminals are connected in common, when integrated, this has the effect of reducing the semiconductor chip area. Figure 2 shows the oscillation circuit of the present invention. 50 indicates the integrated circuit part, and 51 to 5
7 is an external connection terminal, 70 is a mixer that performs a frequency conversion operation, 71 is a buffer amplifier, and 72 is an oscillation operating part. In the embodiment shown in FIG. 1, the first and 20th FEs 71.2
Priest to a certain part.

74 is a negative feedback circuit, a resonator including the resonator 6, and 75 is a buffer amplifier for amplifying the oscillation signal.

In FIG. 2, a high frequency signal is input to terminals 54, 55, amplified by a buffer amplifier 71, frequency converted by a mixer 70 using an oscillation signal from a buffer amplifier 73, and a converted signal is output from terminals 56, 57. Ru. In this example structure, the buffer amplifier 71 and the mixer 70 can also be constituted by FETs, and there is an advantage that a frequency conversion circuit block which is an integrated circuit with good distortion characteristics can be obtained.

FIG. 5 shows a characteristic diagram of the embodiment of the present invention shown in FIG.
This figure shows the oscillation noise and oscillation signal output level when oscillation is performed. Oscillation noise is 50K from the oscillation signal
The frequency detuned by Hz is good at about -105 dBc/Hz, and the oscillation signal is also about -12 dBm.

Note that by grounding the gates of the second and first FETs 2 with resistors, it is possible to suppress abnormal oscillations in the second and first FETs 2.

FIG. 4 shows another embodiment of the present invention, and parts that perform the same operations as the embodiment of FIG. In Figure 4, 15 is an FET.

16.17 is a bias resistance. 10th F E T1
and the second Fh:T2 have their gates grounded and their sources commonly connected to the drain of the constant current source FET 15. A bias resistor 17 is connected between the drains of the second and first FETs 2 and the power supply Vce. As the source current of the first FET 1 changes due to the oscillation operation, the source currents of the second and first FETs 2 also change, and an oscillation signal is extracted from the drain. In this example as well, the second FET 2 is used, and the drain current is also the same as that of the first FET.
, the first FET 1 is placed one above the other, thereby reducing the influence on the 10th FE'l'10 source which performs oscillation operation. In this embodiment, since no FET is added in parallel with the drain to which the resonator 5 is connected, the Q of the resonant circuit is
Therefore, it is possible to provide an oscillation circuit with less oscillation noise and no decrease in oscillation noise. In this embodiment, the source of FET 1.2 is connected to a constant current source, but the same effect can be obtained by using a resistor. In this embodiment as well, it is possible to use an FET whose gate and source are commonly connected, and when it is integrated into an integrated circuit, it has the effect of reducing the semiconductor chip area.

〔Effect of the invention〕

As explained above, according to the present invention, an oscillation circuit with a grounded gate structure in which the gate terminal of the FET is grounded to earth potential is used to reduce low frequency noise that is a cause of oscillation noise. Alternatively, by using an FET for buffer amplification whose sources are commonly connected to reduce the influence on the resonant circuit and prevent a drop in the Q of the resonant circuit, it is suitable for integration and has low oscillation noise. A voltage-controlled variable oscillator circuit using FETs can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a block diagram of a frequency conversion circuit to which the oscillation circuit of the present invention is applied, and FIG. 3 is a characteristic diagram of the circuit shown in FIG. 1. FIG. 4 is a circuit diagram showing a second embodiment of the present invention. 1...first, first FET. 2...Second FET. 5...Resonator? ...Variable capacitance diode. 70...Mixer. 73...Buffer amplifier. 2-$2AFE AJ, 71--2#J crawl mko〉de〉Second section % jl th] Key 4th figure, jl l;σ

Claims (1)

[Claims] 1. Ground the gate terminal of the first FET to earth potential,
A feedback capacitor is connected between the drain and source terminals and between the source and ground potential, and a variable resonant circuit is connected to the drain, and further, to the drain terminal of the first FET,
An oscillation circuit characterized in that drain terminals of second FETs having a gate width narrower than that of the first FET are commonly connected, and an oscillation signal is extracted from the source terminal of the second FET.