JPH0272029U - - Google Patents

Info

Publication number
JPH0272029U
JPH0272029U JP1988151432U JP15143288U JPH0272029U JP H0272029 U JPH0272029 U JP H0272029U JP 1988151432 U JP1988151432 U JP 1988151432U JP 15143288 U JP15143288 U JP 15143288U JP H0272029 U JPH0272029 U JP H0272029U
Authority
JP
Japan
Prior art keywords
register
output
cpu
digital
analog converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988151432U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988151432U priority Critical patent/JPH0272029U/ja
Publication of JPH0272029U publication Critical patent/JPH0272029U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例を示すブロツク図、第
2図は第1図に示す要部の詳細を示す図、第3図
及び第4図はそれぞれ従来例の構成を示す図であ
る。 1……CPU、2……キーボードKB、3……
主記憶装置MMU、6……レジスタREG、8…
…デイジタル・アナログコンバータD/A。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing details of the main parts shown in FIG. 1, and FIGS. 3 and 4 are diagrams showing the configuration of a conventional example. 1...CPU, 2...Keyboard KB, 3...
Main memory MMU, 6...Register REG, 8...
...Digital/analog converter D/A.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 発音体の音量データが設定されるレジスタと、
特定のキー入力を検出することにより音量の増減
指示であることを認識し、上記レジスタに対し適
当な値を設定するプログラムが格納されるメモリ
と、発振器出力とCPUから与えられる発音許可
信号との論理積出力によりエネーブルされ、上記
レジスタに設定されたデータに応じたレベルの信
号を出力するデイジタル・アナログコンバータと
を具備することを特徴とする電子機器。
A register in which the volume data of the sounding body is set,
A memory that stores a program that recognizes a volume increase/decrease instruction by detecting a specific key input and sets an appropriate value to the above register, and a sound generation enable signal given from the oscillator output and the CPU. An electronic device comprising: a digital-to-analog converter that is enabled by an AND output and outputs a signal at a level corresponding to data set in the register.
JP1988151432U 1988-11-21 1988-11-21 Pending JPH0272029U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988151432U JPH0272029U (en) 1988-11-21 1988-11-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988151432U JPH0272029U (en) 1988-11-21 1988-11-21

Publications (1)

Publication Number Publication Date
JPH0272029U true JPH0272029U (en) 1990-06-01

Family

ID=31425473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988151432U Pending JPH0272029U (en) 1988-11-21 1988-11-21

Country Status (1)

Country Link
JP (1) JPH0272029U (en)

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