JPH0273605A - Laminated type varistor - Google Patents

Laminated type varistor

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Publication number
JPH0273605A
JPH0273605A JP22585188A JP22585188A JPH0273605A JP H0273605 A JPH0273605 A JP H0273605A JP 22585188 A JP22585188 A JP 22585188A JP 22585188 A JP22585188 A JP 22585188A JP H0273605 A JPH0273605 A JP H0273605A
Authority
JP
Japan
Prior art keywords
varistor
electrodes
glass powder
leakage current
oxygen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22585188A
Other languages
Japanese (ja)
Inventor
Hiroaki Taira
浩明 平
Kazuyoshi Nakamura
和敬 中村
Yasunobu Yoneda
康信 米田
Yukio Sakabe
行雄 坂部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP22585188A priority Critical patent/JPH0273605A/en
Publication of JPH0273605A publication Critical patent/JPH0273605A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent lack of oxygen at the time of baking, to reduce a leakage current and to improve reliability by alternately laminating varistor layers and inner electrodes, and adding glass powder into the electrodes. CONSTITUTION:Varistor layers 2 made of ZnO ceramics and inner electrodes 3 made of Ag-Pd alloy mixed with glass powder are alternately laminated. It is integrally sintered as a sintered material 4, and outer electrodes 5 are formed at the left and right end faces 4a, 4b. One end faces 3a of the electrodes 3 are alternately exposed with the end faces 4a, 4b of the sintered material 4 to be connected to the electrodes 5, and the other parts are sealed in the material 4. Thus, the glass powder is mixed with the electrodes 3 to avoid a decrease in oxygen concentration at the time of baking and temperature fall, to decrease a leakage current, and to improve reliability.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電圧非直線性抵抗として機能する積層型バリ
スタに関し、特に内部電極近傍領域での酸素濃度低下に
よる漏れ電流を低減して、部品の信鯨性を向上できるよ
うにした構造に関する。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a multilayer varistor that functions as a voltage nonlinear resistor, and in particular reduces leakage current due to a decrease in oxygen concentration in the region near the internal electrode, thereby improving the performance of components. It relates to a structure that can improve the credibility of the system.

〔従来の技術〕[Conventional technology]

一般に、バリスタは、印加電圧に応じて抵抗値が非直線
的に変化する抵抗体素子であり、電子回路に過電圧が加
わるのを防止するためのサージ吸収素子として採用され
ている。このようなバリスタとして、従来、第4図に示
すような直方体状の積層型バリスタがある(特公昭58
−23921号公報参照)、この積層型バリスタ10は
、バリスタ層11と内部電極12とを交互に積層して一
体焼結するとともに、該焼結体13の左、右端面13a
。
Generally, a varistor is a resistor element whose resistance value changes non-linearly depending on an applied voltage, and is used as a surge absorption element to prevent overvoltage from being applied to an electronic circuit. Conventionally, as such a varistor, there is a rectangular parallelepiped laminated type varistor as shown in Fig. 4 (Japanese Patent Publication No. 58
-23921), this multilayer varistor 10 has varistor layers 11 and internal electrodes 12 alternately stacked and integrally sintered, and left and right end surfaces 13a of the sintered body 13.
.

13bに外部電極14を形成して構成されている。An external electrode 14 is formed on 13b.

またこの外部電極14には、上記焼結体13の左。Further, this external electrode 14 has a portion on the left side of the sintered body 13 .

右端面13a、13bに交互に露出された内部電極12
の一端面12aが接続されている。
Internal electrodes 12 alternately exposed on right end surfaces 13a and 13b
One end surface 12a of the two is connected.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、積層型バリスタにおいては、焼成する際の降
温過程でバリスタ層内に酸素を供給する必要がある。と
ころが上記従来のバリスタでは、バリスタ層と内部電極
層とが積層状態であり、バリスタ層の厚みが薄い状態で
あるという条件と相まってバリスタ層の内部電極の近傍
領域部分の酸素濃度を低下させるという問題点がある。
By the way, in a laminated varistor, it is necessary to supply oxygen into the varistor layer during the temperature-lowering process during firing. However, in the conventional varistor described above, the varistor layer and the internal electrode layer are in a laminated state, and this combined with the condition that the thickness of the varistor layer is thin leads to a problem that the oxygen concentration in the region near the internal electrode of the varistor layer decreases. There is a point.

その結果、漏れ電流が大きくなり、ひいては消費電力が
増加し、また熱暴走の原因となるという問題が生・しる
、また、しきい値電圧をIOV以下とする場合のように
、バリスタ層が薄いものほど酸素欠乏の割合が大きくな
るため、漏れ電流が増大する。
As a result, leakage current increases, power consumption increases, and thermal runaway occurs. The thinner the material, the greater the rate of oxygen depletion, which increases the leakage current.

本発明の目的は、焼成時における酸素欠乏を防止して、
漏れ電流を低減でき、信鯨性を向上できる積層型バリス
タを提供することにある。
The purpose of the present invention is to prevent oxygen deficiency during firing,
An object of the present invention is to provide a multilayer varistor that can reduce leakage current and improve reliability.

〔問題点を解決するための手段〕[Means for solving problems]

本件発明者らは、上記降温時における酸素欠乏を回避す
るために種々検討したところ、上記内部電極内に、該電
極の拡散を阻止できる物質を含存させればよいことに着
目し、このような物質としてガラス成分が最適であるこ
とを見出した。ここで、積層型セラミクスコンデンサに
おいては、ガラス成分を添加するとこれがセラミクス部
分に拡散して誘電率を低下させる等の悪影響を与えるこ
とが知られている。この点から積層型バリスタにおいて
も、内部電極にガラス成分を混合添加すると何らかの悪
影響が生じると考えられ、従って従来内部電極にガラス
成分を添加するという発想はなかった。ところが、本件
発明者らが検討を重ねたところ、上記積層型バリスタに
ガラス成分を採用しても、悪影響を与えることはなく、
かつ内部電極の拡散を防止できることが判明し、これに
より本発明を成したものである。
The inventors of the present invention have conducted various studies to avoid the oxygen deficiency during the temperature drop, and have found that it is sufficient to include a substance in the internal electrode that can prevent the diffusion of the electrode. We have found that a glass component is the most suitable material. It is known that when a glass component is added to a multilayer ceramic capacitor, it diffuses into the ceramic portion and has an adverse effect such as lowering the dielectric constant. From this point of view, even in the case of a laminated type varistor, it is thought that mixing and adding a glass component to the internal electrodes would cause some adverse effects, and therefore, conventionally there was no idea of adding a glass component to the internal electrodes. However, after repeated studies by the inventors of the present invention, it was found that even if glass components were used in the above-mentioned laminated varistor, there would be no adverse effect.
It has also been found that diffusion of the internal electrodes can be prevented, and the present invention has been completed thereby.

そこで本発明は、バリスタ層と内部電極とを交互に積層
してなる積層型バリスタにおいて、上記内部電極内にガ
ラス粉末を添加したことを特徴としている。
Therefore, the present invention is a multilayer varistor in which varistor layers and internal electrodes are alternately stacked, and is characterized in that glass powder is added to the internal electrodes.

ここで、ガラス粉末としては、B、Si及びPb、Bl
、Znのうち少なくとも2種類以上含むものを採用する
のが望ましい、また、上記ガラス粉末の添加量としては
、内部電極用に採用される金属に対して0.1〜20w
 t%の範囲が望ましく、これは上記範囲以下では漏れ
電流低減の効果が得られ難く、またこれ以上添加すると
非直線係数の低下を招くからである。
Here, as the glass powder, B, Si, Pb, Bl
It is desirable to use a glass powder containing at least two types of , Zn, and the amount of the glass powder added is 0.1 to 20 w with respect to the metal used for the internal electrode.
A range of t% is desirable because below the above range it is difficult to obtain the effect of reducing leakage current, and adding more than this will result in a decrease in the nonlinear coefficient.

〔作用〕[Effect]

本発明に係る積層型バリスタによれば、内部電極にガラ
ス粉末を混合したので、焼成降温時における酸素濃度の
低下を回避できる。即ち、上記ガラス粉末は焼成温度よ
り軟化温度が低いことから、焼成する際にガラス粉末が
内部電極の金属を極薄い膜で包むこととなる。従って、
降温工程では、上記ガラス粉末が電極金属に酸素を与え
ることとなり、従って該金属がセラミクスから酸素を奪
うことはな(、その結果セラミクス粒界相が還元される
のを防止でき、これによりバリスタ層への酸素供給が補
償され、酸素欠乏を回避できる。その結果、漏れ電流を
低減でき、ひいては消費電力熱暴走の問題等を回避でき
る。
According to the multilayer varistor according to the present invention, since glass powder is mixed into the internal electrodes, a decrease in oxygen concentration during firing and cooling can be avoided. That is, since the glass powder has a softening temperature lower than the firing temperature, the glass powder wraps the metal of the internal electrode in an extremely thin film during firing. Therefore,
In the temperature cooling process, the glass powder gives oxygen to the electrode metal, so that the metal does not deprive the ceramic of oxygen (as a result, the ceramic grain boundary phase is prevented from being reduced, and this prevents the varistor layer from being reduced). The supply of oxygen to the fuel cell is compensated, and oxygen deficiency can be avoided.As a result, leakage current can be reduced, and problems such as power consumption thermal runaway can be avoided.

〔実施例〕〔Example〕

以下、本発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第1図ないし第3図は本発明の一実施例による積層型バ
リスタを説明するための図である。
1 to 3 are diagrams for explaining a multilayer varistor according to an embodiment of the present invention.

図において、1は本実施例の積層型バリスタであり、こ
れは直方体状のもので、ZnO系セラミクスからなるバ
リスタ層2と、ガラス粉末が混合されたAg−Pd合金
からなる内部電極3とを交互に積層し、これを一体焼結
してなる焼結体4の左、右端面4a、4bに外部電極5
を形成して構成されている。また、上記内部電極3の一
端面3aは、交互に上記焼結体4の両端面4a、4bに
露出して上記外部電極5に接続されており、他の部分は
焼結体4内に封入されている。
In the figure, numeral 1 denotes the multilayer varistor of this embodiment, which has a rectangular parallelepiped shape and includes a varistor layer 2 made of ZnO-based ceramics and an internal electrode 3 made of an Ag-Pd alloy mixed with glass powder. External electrodes 5 are provided on the left and right end surfaces 4a and 4b of the sintered body 4, which is formed by laminating the layers alternately and sintering them together.
It is composed of Further, one end surface 3a of the internal electrode 3 is alternately exposed to both end surfaces 4a and 4b of the sintered body 4 and connected to the external electrode 5, and the other portion is enclosed within the sintered body 4. has been done.

次に本実施例の積層型バリスタ1を製造する方法につい
て説明する。
Next, a method for manufacturing the multilayer varistor 1 of this embodiment will be described.

■ まず、Z n O(96,0+mo 11%)、 
B l x Os (1゜5−01%)、Mn0(1,
0moj!%)、 Co t 0s(0+5 n。
■ First, Z n O (96,0+mo 11%),
B l x Os (1°5-01%), Mn0 (1,
0moj! %), Co t 0s (0+5 n.

1%)、T i 0x(1,0son%)を混合してな
るセラミクス材料に、Bt Os 、S loz 、P
bO,ZnOからなるガラス成分を5wt%加えて原料
とし、これに有機バインダーを混合して、ドクターブレ
ード法により厚さ30μ−のグリーンシートを形成した
後、該グリーンシートを矩形状に切断して、多数のバリ
スタ層2を作成する。
Bt Os , S loz , P
A glass component consisting of bO and ZnO was added at 5 wt% as a raw material, and an organic binder was mixed with this to form a green sheet with a thickness of 30μ by a doctor blade method.The green sheet was then cut into rectangular shapes. , a large number of varistor layers 2 are created.

■ 一方、ptにビヒクルを混合してなるベーストに、
Bt 0s=S i Ox等からなるガラス粉末を添加
して電極ペーストを作成する。次に、上記バリスタ層2
の上面にこの電極ペーストをスクリーン印刷して内部電
極3を形成する。この場合、該内部電極3の一端面3a
のみがバリスタ層2の外縁まで延び、他の端面ば内方に
位置するようにする。
■ On the other hand, baset made by mixing PT with vehicle,
An electrode paste is created by adding glass powder such as Bt 0s=S i Ox. Next, the varistor layer 2
The internal electrode 3 is formed by screen printing this electrode paste on the upper surface of the . In this case, one end surface 3a of the internal electrode 3
Only one end face extends to the outer edge of the varistor layer 2, and the other end face is located inward.

■ 次に、第3図に示すように、上記バリスタ層2と内
部電極3とが交互に重なり、かつ内部電極3の一端面3
aがバリスタ層2の両端面に交互に露出するように積層
し、さらにこの積層体の上。
■Next, as shown in FIG. 3, the varistor layers 2 and internal electrodes 3 are alternately overlapped, and
The varistor layer 2 is laminated so that a is alternately exposed on both end faces of the varistor layer 2, and further on top of this laminate.

下面にダミーとしてのセラミクスJW7を重ね、これを
プレスで加圧、圧着して積層体を形成する。
Ceramics JW7 as a dummy is layered on the lower surface, and this is pressed and bonded with a press to form a laminate.

するとこれにより、第1図に示すように、内部電極3の
一端面3aのみが積層体の左、右側面の外方に露出し、
残りの部分はバリスタ層2内に完全に埋設されることと
なる。
Then, as shown in FIG. 1, only one end surface 3a of the internal electrode 3 is exposed to the outside of the left and right side surfaces of the laminate.
The remaining portion will be completely buried within the varistor layer 2.

■ そして、上記積層体を空気中にて900−1300
℃で加熱焼成し、焼結体4を得る。この焼成工程におい
て、内部電8i+3内のガラス粉末が軟化して該電極3
を構成する金属粒子の表面部分を覆うこととなり、従っ
て降温時に上記金属の粒子がセラミクス中の酸素を奪う
ことはなく、セラミクスへの酸素供給を補償し、内部電
極3近傍領域の変質を防止することとなる。
■ Then, the above laminate was placed in the air at a temperature of 900-1300
C. to obtain a sintered body 4. In this firing process, the glass powder in the internal electrode 8i+3 is softened and the electrode 3
Therefore, when the temperature falls, the metal particles do not take away oxygen from the ceramics, thereby compensating the supply of oxygen to the ceramics and preventing deterioration of the area near the internal electrodes 3. That will happen.

■ しかる後、上記焼結体4の、内部電極3の一端面3
aが露出された左、右端面4a、4bにAgを主体とし
てPdを添加してなるペーストを塗布した後焼き付けて
外部電極5を形成する。
■ After that, one end surface 3 of the internal electrode 3 of the sintered body 4 is
External electrodes 5 are formed by applying a paste mainly composed of Ag and adding Pd to the left and right end surfaces 4a and 4b where the portion a is exposed, and then baking the paste.

次に本実施例の作用効果について説明する。Next, the effects of this embodiment will be explained.

本実施例の積層型バリスタ1によれば、内部電極3に降
温時の金属粒子によるセラミクス粒界相の還元を阻止す
るガラス粉末を混合したので、酸素濃度の低下を防止で
き、その結果、漏れ電流を大幅に低減でき、消費電力の
増大を回避できるとともに、熱暴走の危険性を小さくで
きる。
According to the multilayer varistor 1 of this embodiment, the internal electrode 3 is mixed with glass powder that prevents the reduction of the ceramic grain boundary phase by metal particles when the temperature decreases, so it is possible to prevent a decrease in oxygen concentration, and as a result, leakage can be prevented. The current can be significantly reduced, an increase in power consumption can be avoided, and the risk of thermal runaway can be reduced.

次に、本実施例の効果をf!認するために行った実験結
果について説明する。
Next, we will discuss the effects of this embodiment on f! We will explain the results of experiments conducted to confirm this.

この実験では、第1表に示すように、BtOsSiOz
  PbO系(第1欄A) 、Bt O。
In this experiment, as shown in Table 1, BtOsSiOz
PbO-based (column 1 A), BtO.

5tot BitOs系(第2欄B) 、B、○。5tot BitOs system (second column B), B, ○.

−3i Ox −P bo−B it○、系(第3欄C
)、Bx Os  S ioz  ZnO系(第4欄D
)からなる4種類のガラス粉末を採用し、この各ガラス
粉末を上記ptペースト内にそれぞれ0.01〜30w
 t%の範囲内で添加し、上述の製造方法により積層型
バリスタを作成した。そして、各積層型バリスタのV+
−A (素子そのもののバリスタ電圧)、非直線係数α
(α−1/ 1ogCVl@A / V@、IIIA 
)により求めた)、及び漏れ電流(D、C,3Vを印加
したときに流れる電流値)を測定した。また、比較する
ために従来の内部tiにガラス粉末を添加していない積
層型バリスタについても同様の測定を行った。
-3i Ox -P bo-B it○, system (third column C
), Bx Os Sioz ZnO system (column 4 D
), and each of these glass powders was added to the above PT paste at 0.01 to 30 w.
A multilayer varistor was produced by the above-mentioned manufacturing method by adding within the range of t%. Then, V+ of each laminated varistor
−A (varistor voltage of the element itself), nonlinear coefficient α
(α-1/1ogCVl@A/V@, IIIA
), and leakage current (D, C, current value that flows when 3V is applied) was measured. Further, for comparison, similar measurements were performed on a conventional multilayer varistor in which no glass powder was added to the internal Ti.

第2表にその結果を示す、同表からも明らがなように、
従来試料ではVIIIA+  αは本来の特性が得られ
ているものの、漏れ電流は2μAと大きくなっている。
The results are shown in Table 2.As is clear from the table,
In the conventional sample, although the original characteristics of VIIIA+α are obtained, the leakage current is as large as 2 μA.

また、本実施例試料A−Dにおいてもガラス粉末の添加
量が0.01wt%と少ない場合は、漏れ電流は2μA
と大きく低減効果が得られていない、ところが、この添
加量が0.1 wt%を越えると、いずれの実施例試料
A−Dにおいても漏れ電流は0.5μ八以下と大幅に低
減していることがわかる。一方、上記添加量が3Qwt
%を越えると、漏れ電流低減効果は得られているものの
、αが10〜15と低下している。従って、この実験か
ら、上記ガラス粉末の添加量は0.1〜20IIlt%
内にすることが望ましいといえる。
Also, in samples A to D of this example, when the amount of glass powder added was as small as 0.01 wt%, the leakage current was 2 μA.
However, when this addition amount exceeds 0.1 wt%, the leakage current is significantly reduced to 0.5 μ8 or less in all Example samples A-D. I understand that. On the other hand, the above addition amount is 3Qwt
%, the leakage current reduction effect is obtained, but α is reduced to 10 to 15. Therefore, from this experiment, the amount of the glass powder added is 0.1 to 20 IIlt%.
It can be said that it is desirable to keep it within the limits.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明に係る積層型バリスタによれば、内
部電極内にガラス粉末を添加したので、焼成降温時にお
ける酸素欠乏を防止でき、漏れ電流を低減して信鯨性を
向上できる効果がある。
As described above, according to the multilayer varistor of the present invention, since glass powder is added to the internal electrode, it is possible to prevent oxygen depletion during cooling during firing, reduce leakage current, and improve reliability. be.

第 表No. table

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は本発明の一実施例による積層型バ
リスタを説明するためのものであり、第1図はその断面
図、第2図はその斜視図、第3図はその分解斜視図、第
4図は従来の積層型バリスタを示す断面図である。 図において、1は積層型バリスタ、2はバリスタ層、3
は内部電極である。
1 to 3 are for explaining a multilayer varistor according to an embodiment of the present invention, FIG. 1 is a sectional view thereof, FIG. 2 is a perspective view thereof, and FIG. 3 is an exploded perspective view thereof. 4 are cross-sectional views showing a conventional multilayer varistor. In the figure, 1 is a multilayer varistor, 2 is a varistor layer, and 3 is a multilayer varistor.
is the internal electrode.

Claims (1)

【特許請求の範囲】[Claims] (1)バリスタ層と内部電極とを交互に積層してなり、
電圧非直線性抵抗として機能する積層型バリスタにおい
て、上記内部電極内にガラス粉末を添加したことを特徴
とする積層型バリスタ。
(1) Consisting of alternating layers of varistor layers and internal electrodes,
A multilayer varistor that functions as a voltage nonlinear resistor, characterized in that glass powder is added to the internal electrode.
JP22585188A 1988-09-08 1988-09-08 Laminated type varistor Pending JPH0273605A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22585188A JPH0273605A (en) 1988-09-08 1988-09-08 Laminated type varistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22585188A JPH0273605A (en) 1988-09-08 1988-09-08 Laminated type varistor

Publications (1)

Publication Number Publication Date
JPH0273605A true JPH0273605A (en) 1990-03-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP22585188A Pending JPH0273605A (en) 1988-09-08 1988-09-08 Laminated type varistor

Country Status (1)

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JP (1) JPH0273605A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56147406A (en) * 1980-04-17 1981-11-16 Matsushita Electric Industrial Co Ltd Method of manufacturing laminated voltage nonlinear resistor
JPS63119504A (en) * 1986-11-07 1988-05-24 松下電器産業株式会社 Manufacturing method of laminated chip varistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56147406A (en) * 1980-04-17 1981-11-16 Matsushita Electric Industrial Co Ltd Method of manufacturing laminated voltage nonlinear resistor
JPS63119504A (en) * 1986-11-07 1988-05-24 松下電器産業株式会社 Manufacturing method of laminated chip varistor

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