JPH0273848U - - Google Patents
Info
- Publication number
- JPH0273848U JPH0273848U JP15314088U JP15314088U JPH0273848U JP H0273848 U JPH0273848 U JP H0273848U JP 15314088 U JP15314088 U JP 15314088U JP 15314088 U JP15314088 U JP 15314088U JP H0273848 U JPH0273848 U JP H0273848U
- Authority
- JP
- Japan
- Prior art keywords
- data
- serial
- parallel
- synchronization
- conversion means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims 4
- 238000000034 method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案の第１の実施例のブロツク図、
第２図は本考案の第２の実施例のブロツク図、第
３図は一般的なテレメトリデータであるシリアル
データのフオーマツト図である。
１……シフトレジスタ、２……高速メモリ、３
……データスイツチ、４……同期検出部、５……
制御部、６……ラツチ回路、１０……クロツク、
２０……シリアルデータ、３０……パラレルデー
タ（８ビツト）、４０……タイミング信号、５０
……書き込み制御信号、６０……読み出し制御信
号、７０……パラレルデータ、８０……同期タイ
ミング信号、９０……制御信号、１００……入力
端子、２００……出力端子。
FIG. 1 is a block diagram of the first embodiment of the present invention;
FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a format diagram of serial data, which is general telemetry data. 1...Shift register, 2...High speed memory, 3
...Data switch, 4...Synchronization detection unit, 5...
Control unit, 6...Latch circuit, 10...Clock,
20... Serial data, 30... Parallel data (8 bits), 40... Timing signal, 50
...Write control signal, 60...Read control signal, 70...Parallel data, 80...Synchronization timing signal, 90...Control signal, 100...Input terminal, 200...Output terminal.
Claims (1)
データに変換するデータフオーマツトの同期確立
方式において、入力されるシリアルデータを一時
記憶しパラレルデータとして出力するシリアル・
パラレル変換手段と、前記シリアル・パラレル変
換手段のパラレルデータを記憶する高速メモリと
、前記高速メモリから低速で読み出されたデータ
に含まれる一定の繰返し周期の同期コードを検出
する第１の手段ならびに前記第１の手段で検出さ
れた同期コードをもとに前記シリアル・パラレル
変換手段の出力のパラレルデータに含まれる同期
コードを検出する第２の手段のうち少なくとも第
１の手段を備えた同期検出手段と、前記同期検出
手段で検出された同期信号と外部から入力される
クロツク信号とにより前記シリアル・パラレル変
換手段にパラレルデータのタイミング信号を供給
する制御手段とを備えたことを特徴とする同期確
立方式。 In a data format synchronization establishment method that converts serial data input from the outside into parallel data, serial data is temporarily stored and output as parallel data.
a parallel conversion means, a high-speed memory for storing parallel data of the serial-to-parallel conversion means, a first means for detecting a synchronization code with a constant repetition period contained in data read out at low speed from the high-speed memory; Synchronization detection comprising at least a first means of second means for detecting a synchronization code included in parallel data output from the serial-to-parallel conversion means based on the synchronization code detected by the first means. and control means for supplying a timing signal of parallel data to the serial-to-parallel conversion means based on the synchronization signal detected by the synchronization detection means and a clock signal input from the outside. Establishment method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15314088U JPH0273848U (en) | 1988-11-24 | 1988-11-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15314088U JPH0273848U (en) | 1988-11-24 | 1988-11-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0273848U true JPH0273848U (en) | 1990-06-06 |
Family
ID=31428709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15314088U Pending JPH0273848U (en) | 1988-11-24 | 1988-11-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0273848U (en) |
-
1988
- 1988-11-24 JP JP15314088U patent/JPH0273848U/ja active Pending
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