JPH02742U - - Google Patents
Info
- Publication number
- JPH02742U JPH02742U JP1988077428U JP7742888U JPH02742U JP H02742 U JPH02742 U JP H02742U JP 1988077428 U JP1988077428 U JP 1988077428U JP 7742888 U JP7742888 U JP 7742888U JP H02742 U JPH02742 U JP H02742U
- Authority
- JP
- Japan
- Prior art keywords
- package
- main surfaces
- semiconductor device
- lead
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａ，ｂおよびｃはそれぞれ本考案の一実
施例を示す半導体装置の平面図、Ａ−Ａ′断面図
および側面図、第２図ａおよびｂはそれぞれ従来
半導体装置の平面図および側面図である。
１……リード、２……パツケージ。
Figures 1a, b and c are a plan view, A-A' sectional view and side view of a semiconductor device showing an embodiment of the present invention, respectively, and Figures 2a and b are a plan view and side view of a conventional semiconductor device, respectively. It is a diagram. 1...Lead, 2...Package.
Claims (1)
れ、且つ、前記各リードはパツケージの前記２主
面とそれぞれ同一平面に一体化され露出されてい
ることを特徴とする半導体装置。 A semiconductor device characterized in that a plurality of leads are led out on two main surfaces of a package, and each lead is integrated and exposed on the same plane as the two main surfaces of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988077428U JPH02742U (en) | 1988-06-10 | 1988-06-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988077428U JPH02742U (en) | 1988-06-10 | 1988-06-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02742U true JPH02742U (en) | 1990-01-05 |
Family
ID=31302413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988077428U Pending JPH02742U (en) | 1988-06-10 | 1988-06-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02742U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006287131A (en) * | 2005-04-04 | 2006-10-19 | Sony Corp | Semiconductor package and manufacturing method thereof |
-
1988
- 1988-06-10 JP JP1988077428U patent/JPH02742U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006287131A (en) * | 2005-04-04 | 2006-10-19 | Sony Corp | Semiconductor package and manufacturing method thereof |