JPH0274879A - Ic testing apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an IC testing device, and in particular, it converts test pattern data sequentially generated in a predetermined arrangement into one or more types of arrangement order, and converts these test pattern data into one or more types of arrangement order. The present invention relates to enabling one data array to be selectively applied as test data to an IC under test.

[Prior Art] In an IC testing device, as an example of testing an internal logic circuit such as a logic IC or a memory IC, multiple types of test pattern data consisting of multiple bits are used as test data to input a predetermined signal of the IC under test. There is a code error check that confirms the normality of the IC under test by applying a signal to a bin and detecting a signal output from a signal output bin corresponding to the input bin. By detecting the output signal of the IC under test with a detection circuit and comparing and checking the detected data with the test data applied to the IC under test,
Check whether there is a code error in the detected data. Based on the result of this code error check, the quality of the internal logic circuit of the IC under test is determined. If a code error is found in the detected data, the IC under test corresponding to the code error location
It is determined that there is a fault in the internal logic circuit. In this case, in order to achieve code error accuracy, interleaved test data obtained by converting the test pattern data into a predetermined arrangement order is used.

Note that, as is well known, interleaving can also be realized by, for example, storing data input to a bank memory as shown in FIG. 2 in a predetermined arrangement in each bank. Such an interleaved memory is a memory consisting of a plurality of storage areas in which data can be stored such that adjacent addresses are different addresses. For example, as shown in FIG. 3, input data D1 is stored in banks 1 to 4 in a format shifted by a predetermined unit under the control of the control unit 5. When reading data from the memory, data is read out repeatedly in the order of banks 1 to 4 to obtain data arrayed like data D3.

When testing internal logic circuits such as logic ICs and memory ICs, interleaved data as described above is applied to a predetermined signal input pin of the IC under test, and the detected signal is extracted from the output pin corresponding to the input pin. Detect.

After this detected data is reproduced (referred to as deinterleaving) to the same original data arrangement as before interleaving, the detected data is checked for code errors by comparing it with input data D1 in FIG. 3, for example.

[Problem to be solved by the invention] However, in the conventional IC test device as described above,
Only one type of data array could be applied to the IC under test as test data. Therefore, if it is desired to apply a plurality of types of data arrays to the IC under test as test data, the test operation must be temporarily interrupted and new test data must be set, which is troublesome.

The present invention has been made in view of the above-mentioned points, and is an IC testing device that is capable of sequentially applying a plurality of test data having different data arrangement orders to an IC under test by setting a plurality of types of data arrangement in advance. This is what we are trying to provide.

[Means for Solving the Problems] An IC testing device according to the present invention includes: a pattern data generating means for sequentially generating a plurality of types of test pattern data consisting of a plurality of bits in a predetermined arrangement; array converting means for converting the arrangement order of pattern data provided by the array converting means and providing one or more types of pattern data in different arrays, and one or more types of arrays of the pattern data provided by the array converting means and the pattern; and selecting means for selecting one of the pattern data arrays as provided by the data generating means as test data to be applied to the IC under test. When these functional configurations correspond to the functional blocks in FIG. 1, the pattern data generation means corresponds to the pattern generation section 11, and the array conversion means corresponds to the bank memory 1.
2, and selection means correspond to selectors 13 to 17, respectively.

[The action co-pattern data generating means sequentially generates a plurality of types of test pattern data each consisting of a plurality of bits in a predetermined arrangement. The array conversion means converts the array of pattern data given from the pattern data generation means into one or more types of arrays.

The selection means selects one of one or more types of array of pattern data provided by the array conversion means and one of the array of pattern data as given from the pattern data generation means.
one array is selected as test data to be applied to the IC under test.

For example, if the array conversion means is a bank memory that can store two types of data arrays consisting of four storage areas, the pattern data given from the pattern data generation means will be arranged in a predetermined order for each bank 1 to bank 1. 4
is memorized. An example of the data arrangement in the bank memory is shown in FIG. Next, as the test data to be applied to the IC under test by the selection means, "data D" is selected.
4 from bank 1 and bank 2, or.

Data D5 is read from bank 3 and bank 4 and output.

By setting multiple types of data arrays for the IC under test in advance in this way, multiple types of test data can be used without interrupting the work even during the test. Therefore, even when applying test data of a plurality of types of data arrays to the IC under test and performing a code error check, etc.

It is now possible to use test data in multiple types of data arrangement orders without interrupting test work, and the IC
It can be expected to improve the efficiency of testing work.

[Example] Hereinafter, an example of an IC testing device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of an IC testing device according to the present invention, and shows only the parts directly related to the present invention. The tester 10 includes a control section 21. Pattern data generation circuit 1
1. It consists of a bank memory 12, a detection circuit 19, etc., and operates and manages the entire device.

The control section 21 performs various controls by sending control signals to each section via the control signal line SS, and also controls the entire device and processes various data.

The pattern data generation circuit 11 sequentially generates test pattern data in a predetermined arrangement based on control from the control section 21. The pattern data generated here is given to the bank memory 12 and selectors 16 and 17.

The bank memory 12 is made up of a plurality of n storage areas, and here it is made up of four storage areas. The bank memory 12 stores input test pattern data in one or more arbitrary data arrays under the control of the control section 21. For example, it is possible to store data in the 4-way interleave format shown in FIG. 2 or in the multiple types of 2-way interleave format shown in FIG. When the memory is operated as two sets of 2-way interleaved bank memories as shown in FIG.

An example of the data arrangement stored in the bank memory 12 is shown in FIG. The data stored in banks 1 and 2 and the data stored in banks 3 and 4 are arranged in different data arrays D4. Each is read out as D5.

Note that as the bank memory 12, for example, a RAM that can be read and written at any time may be used.

The selector 13 selects the data array to be read from the bank memory 12 based on the control from the control unit 21, and the selected data is sent to the selector 16.1.
7 is given. The selector 14.15 selects n/2-way interleaved data, and the output data of each selector 14.15 is sent to the selector 16.1.
7 is given. Therefore, the type of interleaved data n
/ Selector 1 to selector n according to the number of 2 ways /
2 is provided. For example, in FIG. 4, 4/2 sets of selectors 14 and 15 are provided. -Bank memory 12
An example of the data arrangement stored in banks 1 to 4 is shown in FIG. in this way,
For example, data D4 is selected by the selector 14 and given to the selectors 16 and 17,
Data D5 is selected by selector 15 and selector 1
Given on 6.17.

The selector 16 selects pattern data D1, data D3 . Data D4 and Data D5
The data to be applied to the IC 20 under test is selected from among the data and output as test data D6.

The signal output from the signal output pin of the IC under test 20 is
The signal is applied to the detection circuit 19 as a signal to be detected via the bus SB. The detection circuit 19 compares and detects a predetermined reference voltage for detection with an input detected signal, and provides the detected data to the control unit 21 . In the control unit 21, the detected data is deinterleaved into data in the same format as the pattern data output from the pattern data generation circuit 11, and then the IC 2
It is compared with the pattern data applied to 0 and a code error check is performed.

The selector 17 selects data to be stored in the fail memory 18 from among the pattern data D1, data D3, data D4, and data D5 inputted from the pattern data generation circuit 11, based on control from the control unit 21.

The data selected here depends on the test content.
It does not have to be the same as the test data D6 to be applied to C20.

The fail memory 18 stores the test data applied to the IC under test 20 under the control of the control unit 21, and when an error occurs in the code error check, the error is stored in the address of the fail memory 18 corresponding to the error location. code is written. As fail memory 18,
For example, it is preferable to use a RAM that can be read and written at any time.

Next, specific operations of each part in the above-described configuration will be described. For example, it is assumed that the bank memory 12 operates in a four-way interleave manner. Pattern data D1 shown in FIG. 3 is applied from the pattern data generation circuit 11 to the bank memory 12 and selectors 16 and 17. IC to be tested: 20 using the pattern data D King as test data D6
, the pattern data D1 is selected by the selector 16 and output to the IC 20.

Further, when storing the pattern data D1 in the fail memory 18, the selector 17 selects the pattern data D1.
1 is selected and output to the fail memory 18.

On the other hand, when applying one type of data array to the IC under test 20 as test data D6, the pattern data generation circuit 1
The pattern data D1 outputted from the bank memory 12 is stored in each bank 1 to 4 of the bank memory 12, as shown in FIG.

Each piece of data stored in the bank memory 12 is read out as data D3 as shown in FIG. Data D3
is selected by the selector 16 and output to the IC under test 20 as test data D6.

Furthermore, the data D3 selected by the selector 17 is
It is output to the fail memory 18.

On the other hand, when the bank memory 12 is set to store two types of data arrays as shown in FIG.
are stored in each bank 1 to 4 of the bank memory 12 as shown in FIG. When applying data D4 as test data D6 to the IC under test 20, data D4 read from bank 1.2 is sent to selector 16.1 via selector 14.
7 is given. The selector 16 selects the data D4 and outputs it to the IC under test 20 as test data D6. Further, when data D4 is to be stored in the fail memory 18 as fail data, the selector 17 selects the data D4 and outputs it to the fail memory 18.

Furthermore, data D5 is set as test data D6 to the IC2 under test.
When applying 0, data D5 read from bank 3.4 is given to selectors 1G and 17 via selector 14. The selector 16 selects the data D5 and outputs it to the IC under test 20 as test data D6.

In addition, in the selector 17, when storing the data D5 in the fail memory 18 as fail data, the data D5 is stored as fail data in the fail memory 18.
5 is selected and output to the fail memory 18.

The test data D6 thus applied to the signal input pin of the IC 20 under test is taken out from the signal output pin of the IC 20 as data to be detected and provided to the detection circuit 19. The data detected by the detection circuit 19 is given to the control section 21, where a code error check as described above is performed. If an error is found, an error code is written to the address of the fail memory 18 corresponding to the error. Then, in the control unit 21, the fail memory 1
The fail data stored in 8 is read out and various data processing is executed.

In this embodiment, a bank memory composed of four storage areas is described as an example, but the present invention is not limited to this embodiment, and a memory composed of any other suitable number of banks may be used. Further, the bank function in the bank memory 12 is not limited to a physical bank function, but may be a memory having a logical bank function. Furthermore, although a memory is used as a means for converting the pattern data arrangement order in this embodiment, any other suitable circuit device other than the memory may be used as long as it has a functional configuration capable of converting the desired data arrangement order. There may be.

[Effects of the Invention] As described above, according to the IC testing device according to the present invention, it is possible to convert multiple types of data arrangement orders, and selectively sequentially transfer test data of a desired data arrangement to an IC under test. Even if multiple types of test data are required during an IC test, there is no need to temporarily interrupt the test work and set new test data again. Test data can be sequentially applied to the IC under test. Therefore, an excellent effect is achieved in that efficiency of IC testing work can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an IC testing device according to the present invention, FIG. 2 is a diagram showing an example of a data arrangement in a memory having one type of data arrangement conversion function consisting of four storage areas, and FIG. The figure is a diagram illustrating an example of the data array in Figure 2, Figure 4 is a diagram illustrating an example of the data array in a memory having two types of data array conversion functions consisting of four storage areas, and Figure 5 is a diagram illustrating an example of the data array in a memory having two types of data array conversion functions consisting of four storage areas. FIG. 2 is a diagram illustrating an example of a data array in FIG. 10...Tester, 11...Pattern data generation section,
12...Bank memory, 13-17...Selector,
18... Fail data memory, 19... Detection circuit, 20... IC under test, 21... Control unit.

Claims (1)

[Scope of Claims] Pattern data generation means for sequentially generating a plurality of types of test pattern data consisting of a plurality of bits in a predetermined arrangement; converting the arrangement order of the pattern data given from the pattern data generation means; Array conversion means for providing a plurality of types of pattern data in different arrangements, respectively; one or more types of arrangement of the pattern data provided by the arrangement conversion means and the pattern data as given from the pattern data generation means; 1. An IC testing device comprising: selection means for selecting one of the arrays as test data to be applied to an IC under test.