JPH027596A - Wiring board with interlayered film element - Google Patents
Wiring board with interlayered film elementInfo
- Publication number
- JPH027596A JPH027596A JP63156932A JP15693288A JPH027596A JP H027596 A JPH027596 A JP H027596A JP 63156932 A JP63156932 A JP 63156932A JP 15693288 A JP15693288 A JP 15693288A JP H027596 A JPH027596 A JP H027596A
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- wiring board
- printed
- layer
- paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
抵抗、コンデンサ等の膜素子を内装した配線基板に関し
、
印刷・焼成を主工程として厚膜回路を内層した配線基板
を形成する場合に、特に、印刷・焼成等の工程中に膜抵
抗素子が酸化、還元等による損傷を受けないようにする
ことを目的とし、
金属基材にホーロー層を形成し、該ホーロー層上に無機
質厚膜導体パターン及び該パターンに接続する所望の厚
膜回路素子を印刷・焼成してなる配線基板上に、絶縁樹
脂層を形成すると共に該絶縁樹脂層を介してビアホール
等で所望により前記導体パターンと該絶縁樹脂層の上に
形成した表面層配線パターンとを接続したことを特徴と
する、膜素子を内層した配線基板を構成する。[Detailed Description of the Invention] [Summary] Regarding wiring boards that have film elements such as resistors and capacitors inside, printing and baking are particularly important when forming wiring boards with thick film circuits as the main process. In order to prevent the film resistance element from being damaged by oxidation, reduction, etc. during the firing process, an enamel layer is formed on the metal base material, and an inorganic thick film conductor pattern and the pattern are formed on the enamel layer. An insulating resin layer is formed on a wiring board formed by printing and firing a desired thick film circuit element to be connected to the conductive pattern and the insulating resin layer, as desired, via a via hole or the like via the insulating resin layer. A wiring board having a film element as an inner layer is constructed, which is characterized in that the film element is connected to a surface layer wiring pattern formed in the above.
本発明は電子回路の配線基板に関し、特に抵抗、コンデ
ンサ等の膜素子を内層した配線基板に関する。The present invention relates to a wiring board for electronic circuits, and more particularly to a wiring board having film elements such as resistors and capacitors in the inner layer.
抵抗、コンデンサ等の膜素子を配線基板の内部に形成し
て、配線基板を多層化する場合に、印刷・焼成等の工程
で膜素子が損傷を受けず、かつ低、コストで実現でき、
用途に応じて融通性のある配線基板が要望される。When film elements such as resistors and capacitors are formed inside a wiring board to make the wiring board multilayered, the film elements are not damaged during processes such as printing and baking, and can be realized at low cost.
A flexible wiring board is required depending on the application.
従来、配線基板内に個別部品である膜素子(抵抗、コン
デンサ等)を構成する場合に、信頼度が高く、産業用、
民生用として広く採用されている方法として、第5図に
示すように、セラミック基板、ホーロー基板等の無a質
の絶縁基板11上に銅(Cu) 、銀パラジウム(Ag
−Pd)、銀プラチナ(Ag−PL)の粉末とガラス質
粉末等よりなる導体ペーストを印刷・焼成し、無機成分
の焼結又は溶融により厚膜導体パターン12を形成し、
この厚膜導体パターン12の所望の位置に酸化ルテニウ
ム(Rust)粉末とガラス質粉末等よりなる抵抗ペー
ス)13を焼成して無機質の膜抵抗素子を形成し、レー
ザー照射等のトリミングによりこの抵抗ペースト(膜抵
抗素子)13の抵抗値の調整を行うものである。Conventionally, when configuring film elements (resistors, capacitors, etc.), which are individual parts, in a wiring board, highly reliable, industrial,
As shown in FIG. 5, as a method widely adopted for consumer use, copper (Cu), silver palladium (Ag
- Printing and firing a conductor paste made of Pd), silver platinum (Ag-PL) powder, glassy powder, etc., and forming a thick film conductor pattern 12 by sintering or melting the inorganic component,
A resistive paste (made of ruthenium oxide (Rust) powder, glassy powder, etc.) 13 is fired at a desired position of the thick film conductor pattern 12 to form an inorganic film resistive element, and this resistive paste is trimmed by laser irradiation or the like. (Membrane resistance element) This is used to adjust the resistance value of 13.
また、この配線基板の多層化にあたっては、第6図に示
すように、導体ペースト12と絶縁体ペースト14を交
互に印刷・焼成し、接続ビア15を設けることにより導
体パターン12と表面層配線パターン16とが接続され
、多層配線が行われる。しかしながら、膜抵抗素子13
上に回路パターン16を設けて膜抵抗素子13を配線基
板の内層に形成することは絶縁体ペース1−14、接続
ビア15、表面層配線パターンを構成する無機質ペース
トの焼成は膜抵抗素子13と同程度温度の焼成温度であ
る為に膜抵抗素子13が酸化或いは還元により変質しな
いよう焼成工程上の考慮が必要で、また抵抗トリミング
上も困難である。In addition, in making this wiring board multilayer, as shown in FIG. 6, conductor paste 12 and insulator paste 14 are alternately printed and fired, and connection vias 15 are provided to form conductor pattern 12 and surface layer wiring pattern. 16 is connected to perform multilayer wiring. However, the film resistance element 13
Forming the membrane resistor element 13 on the inner layer of the wiring board by providing the circuit pattern 16 thereon involves firing the insulator paste 1-14, the connection vias 15, and the inorganic paste constituting the surface layer wiring pattern with the membrane resistor element 13. Since the firing temperatures are about the same, consideration must be given to the firing process so that the film resistance element 13 is not altered by oxidation or reduction, and it is also difficult to trim the resistance.
また、膜抵抗素子として、産業用としては信頼度上不十
分とされている、炭素粉末を樹脂成分の加熱・硬化によ
り成膜するポリマー厚膜抵抗ペーストは、配線導体であ
る炭素粉末が絶縁体と共にポリマーの加熱重合により形
成されたものであるため、後工程での加熱条件及び膜抵
抗素子はサンドプラス、レーザー等のトリミングによっ
て抵抗値の調整を行う必要があり、抵抗膜素子の配線基
板内層化は困難である。In addition, polymer thick film resistance paste, which is formed by heating and curing carbon powder as a resin component, is considered to have insufficient reliability for industrial use as a film resistance element. Since it is formed by heating and polymerizing a polymer, it is necessary to adjust the heating conditions in the subsequent process and the resistance value of the film resistor element by trimming with sand plus, laser, etc., and the inner layer of the wiring board of the resistive film element It is difficult to
また、後工程で焼成加熱条件が厳しくない方法とし感光
性ポリマーを無機質配線基板上に塗布し、無機質配線基
板の絶縁層とし、この感光性ポリマーにホトエツチング
法でビア接続用の穴を設け、その上に無電解メツキ積み
上げ法或いはホトエツチング法等により所望の配線パタ
ーンを形成する方法が、特に、デジタル高速信号の回路
において、絶縁層の低誘電率化の目的で発案されている
。しかし、この方法は感光性ポリマー、ホトレジスト、
導体のエツチング、塗布或いはメツキの繰り返し工程で
あり、メタライズ、ホトエツチングを主工程とする薄膜
ハイブリッド基板と、印刷・焼成を主工程とする厚膜ハ
イブリッド基板とのコスト比較で公知のように感光性ポ
リマーを用いる方法は、工程が複雑でコスト高となる。In addition, as a method that does not require harsh firing conditions in the post-process, a photosensitive polymer is coated on an inorganic wiring board to serve as an insulating layer for the inorganic wiring board, and holes for via connections are formed in this photosensitive polymer using a photoetching method. A method of forming a desired wiring pattern thereon by electroless plating or photoetching has been proposed for the purpose of lowering the dielectric constant of an insulating layer, particularly in digital high-speed signal circuits. However, this method uses photosensitive polymers, photoresists,
It is a process of repeating conductor etching, coating, or plating, and it is known that photosensitive polymer The method using this method involves complicated steps and high costs.
また、主としてアルミナ等のセラミックからなる無機質
配線基板は、硬脆材料である為、曲げ、衝撃に弱く、大
型の基板は得にくい。更に配線基板の付加価値向上の為
、基板を折り曲げて筐体としての構造的用途を持たせた
い等、配線基板の多機能化かつ低コスト化の要求が、特
に携帯用電子機器に多くなる状況がある。In addition, since inorganic wiring boards mainly made of ceramics such as alumina are hard and brittle materials, they are susceptible to bending and impact, making it difficult to obtain large boards. Furthermore, in order to increase the added value of wiring boards, there is an increasing demand for multifunctional wiring boards and lower costs, such as bending the board to have a structural purpose as a housing, especially for portable electronic devices. There is.
従って、本発明の第1の課題は、印刷・焼成を主工程と
してW−膜回路を内層した配線基板を形成する場合に、
特に、印刷・焼成等の工程中に膜抵抗素子が酸化、還元
等による損傷を受けないようにした配線基板を提供する
ことである。Therefore, the first problem of the present invention is to form a wiring board with a W-film circuit as an inner layer using printing and baking as the main steps.
In particular, it is an object of the present invention to provide a wiring board in which a film resistance element is not damaged by oxidation, reduction, etc. during printing, baking, and other processes.
本発明の第2の課題は、上記に加え、更に配線基板を例
えば筐体等の構造物の一部として使用可能なように融通
性のある配線基板を提供することである。In addition to the above, a second object of the present invention is to provide a flexible wiring board that can be used as a part of a structure such as a casing.
第1の課題を解決する手段として、本発明によれば、金
属基材にホーロー層を形成し、該ホーロー層上に無機質
厚膜導体パターン及び該パターンに接続する所望の厚膜
回路素子を印刷・焼成してなる配線基板上に、絶縁樹脂
層を形成すると共に該絶縁樹脂層を介してビアホール等
で所望により前記導体パターンと該絶縁樹脂層の上に形
成した表面層配線パターンとを接続したことを特徴とす
る、膜素子を内層した配線基板が提供される。As a means for solving the first problem, according to the present invention, an enamel layer is formed on a metal base material, and an inorganic thick film conductor pattern and a desired thick film circuit element connected to the pattern are printed on the enamel layer.・An insulating resin layer was formed on the baked wiring board, and the conductor pattern and the surface layer wiring pattern formed on the insulating resin layer were connected as desired through the insulating resin layer through via holes, etc. A wiring board having a film element as an inner layer is provided.
また、第2の課題を解決する手段として、金属基材にホ
ーロー層を区分し互いに間隔をあけて印刷・焼成し、ホ
ーロー層上に無a質厚膜回路を形成し、区分された各ホ
ーロー層上の前記厚膜回路を覆うように絶縁樹脂層を形
成し、絶縁樹脂層に形成した配線パターンにより、区分
された各ホーロー層上の前記厚膜回路間を相互に接続し
たことを特徴とする、膜素子を内層した配線基板が提供
される。In addition, as a means to solve the second problem, enamel layers are divided into metal substrates, printed and fired at intervals, and a non-aluminum thick film circuit is formed on the enamel layers, and each divided enamel layer is printed and fired at intervals. An insulating resin layer is formed to cover the thick film circuit on the layer, and the thick film circuits on each divided enamel layer are interconnected by a wiring pattern formed on the insulating resin layer. A wiring board having a film element as an inner layer is provided.
本発明の第1の手段によれば、無機質の焼結成いは溶融
により形成される厚膜回路構成と、樹脂の重合・硬化に
より形成されるポリマー厚膜回路構成は、焼成あるいは
重合時の加熱温度あるいは厚膜回路の耐熱性が大きく隔
たり、無機質の厚膜回路形成後、その上にポリマー厚膜
回路を形成してもその重合温度により無aljt厚膜回
路、なかんず(膜抵抗素子が酸化、還元による損傷を受
けことはない、従って、印刷・焼成を主工程とした、低
コストで製造可能な、配線基板の内層に回路素子を埋設
した多層配線基板を提供することができる。According to the first means of the present invention, a thick film circuit structure in which an inorganic sintered bond is formed by melting, and a polymer thick film circuit structure in which a resin is polymerized and hardened are formed by sintering or heating during polymerization. There is a large difference in temperature or heat resistance of thick film circuits, and even if a polymer thick film circuit is formed on top of an inorganic thick film circuit, the polymerization temperature may cause a non-Aljt thick film circuit, especially (film resistance elements may be oxidized). Therefore, it is possible to provide a multilayer wiring board in which circuit elements are embedded in the inner layer of the wiring board, which is not damaged by reduction and can be manufactured at low cost using printing and baking as the main processes.
また、本発明の第2の手段によれば、ホーロー層を避け
た部分、即ち複数のホーロー層の間隔部分で配線基板を
折り曲げることにより、構造的要素を持たせ筐体の一部
等としての使用が可能となる。Further, according to the second means of the present invention, by bending the wiring board at a portion avoiding the enamel layer, that is, at an interval between a plurality of enamel layers, a structural element can be provided and the wiring board can be used as a part of a casing. It becomes possible to use it.
以下、添付図面を参照して本発明の実施例を詳細に説明
する。Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
第1図は本発明の配線基板の第1実施例であり、鉄又は
アルミニウム等の金属基材1上にガラス質のホーローN
2を所望により印刷・焼成したホーロー層基板に大型集
積回路(LSI) 9及びチップ部品10を搭載・実装
した配線基板の実施例である。FIG. 1 shows a first embodiment of the wiring board of the present invention, in which a vitreous enamel N is placed on a metal base material 1 such as iron or aluminum.
This is an embodiment of a wiring board in which a large integrated circuit (LSI) 9 and a chip component 10 are mounted and mounted on a hollow layer board printed and fired as desired.
第2図は本発明の配線基板の第2実施例であり、金属基
材1上に相互に間隔をあけて区分してガラス質のホーロ
ー層2.2′を形成し、これらのホーロー層2.2′間
をポリマー樹脂層からなる配線パターン7で接続すると
共に、上記ホーロー層2.2′間で折り曲げた配線基板
の実施例である。FIG. 2 shows a second embodiment of the wiring board of the present invention, in which vitreous enamel layers 2 and 2' are formed on a metal substrate 1 by dividing them at intervals. This is an embodiment of a wiring board in which the enamel layers 2 and 2' are connected by a wiring pattern 7 made of a polymer resin layer, and the enamel layers 2 and 2' are bent.
第3図は金属基材1の両面に配線回路を構成し、スルー
ホール31にて相互に接続した実施例である。FIG. 3 shows an embodiment in which wiring circuits are formed on both sides of the metal base material 1 and are interconnected through through holes 31.
第4図は第1図の実施例にかかる配線基板の製造工程を
示す、第4図において、1は金属基材、例えば板厚が1
.2〜2宵lの低炭素鋼で、この基材1上の所望位置に
印刷によりガラス基材よりなるホーローペースト2 (
2’ )を印刷し、溶着させる(a)。その後、厚膜導
体ペースト、例えば銀パラジウム(Ag−Pd)とガラ
スフリントとを混合したペーストを塗布し、所望の厚膜
回路パターン或いは電極3を印刷・焼成する(b)。次
工程で厚膜回路パターン3に接続する所望の位置に厚膜
抵抗ペースト(例えばRu5t)を印刷・焼成し、圧膜
抵抗素子4を形成する(c)。次工程で、厚膜回路パタ
ーン3の多層接続を行う為のビアホール5をrJ−膜回
路パターン3上に印刷・焼成する(d)。FIG. 4 shows the manufacturing process of the wiring board according to the embodiment shown in FIG. 1. In FIG.
.. Enamel paste 2 made of glass base material is printed on the desired position on this base material 1 with 2 to 2 liters of low carbon steel (
2') is printed and welded (a). Thereafter, a thick film conductor paste, for example a paste of a mixture of silver palladium (Ag-Pd) and glass flint, is applied, and a desired thick film circuit pattern or electrode 3 is printed and fired (b). In the next step, a thick film resistor paste (for example, Ru5t) is printed and fired at a desired position to be connected to the thick film circuit pattern 3, thereby forming a piezoelectric film resistor element 4 (c). In the next step, via holes 5 for multilayer connection of the thick film circuit pattern 3 are printed and fired on the rJ-film circuit pattern 3 (d).
次工程で厚膜抵抗素子4をレーザ等でトリミングし、所
望の抵抗値に調整する。次工程で絶縁樹脂材料6を配線
基板全面に印刷・重合しくe)、更に次工程でポリマー
導体ペーストを印刷・重合し、所望の回路パターン7を
成形し、更にその上の所望の位置にハンダレジストペー
スト8を印刷・重合する(f)。回路パターン7を形成
する際は、この回路パターン7がビアホール5を介して
内層の厚膜回路パターン3に接続させる。In the next step, the thick film resistive element 4 is trimmed using a laser or the like to adjust the resistance to a desired value. In the next step, insulating resin material 6 is printed and polymerized on the entire surface of the wiring board (e), and in the next step, polymer conductor paste is printed and polymerized to form the desired circuit pattern 7, and then solder is placed at the desired position on top of the polymer conductor paste. Print and polymerize resist paste 8 (f). When forming the circuit pattern 7, this circuit pattern 7 is connected to the thick film circuit pattern 3 in the inner layer via the via hole 5.
なお、ホーローペースト2、厚膜導体(回路パターン)
3、厚膜抵抗ペースト(抵抗素子)4の焼成温度は、素
材により大きく異なるが約500〜1000℃の範囲で
ある。一方、ポリマー材料(絶縁樹脂材料6、回路パタ
ーン7)の重合温度は約150〜250℃の範囲であり
、厚膜抵抗素子4が配線基板に内層化されても、多層化
工程、即ちポリマー材料の重合の工程で充分基えうる程
度の低い温度範囲である。In addition, enamel paste 2, thick film conductor (circuit pattern)
3. The firing temperature of the thick film resistor paste (resistance element) 4 varies greatly depending on the material, but is in the range of about 500 to 1000°C. On the other hand, the polymerization temperature of the polymer material (insulating resin material 6, circuit pattern 7) is in the range of about 150 to 250°C, and even if the thick film resistor element 4 is internally layered on the wiring board, the multilayer process, i.e., the polymer material This temperature range is low enough to be used in the polymerization process.
また、第1図において、多層化した配線基板の表面回路
パターン7に接続するように大型集積回路(LSI)
9やチップ部品10をハンダペースト上に載せリフロー
ハンダ付けすることにより、固定・実装される。また、
もう一方のホーロー層2゛上にも前記と同様に、厚膜導
体(回路パターン)3、厚膜抵抗ペースト(抵抗素子)
4が印刷・焼成され、かつポリマー材料(絶縁樹脂材料
6、回路パターン7)が重合される。ホーロー層2.2
”間の領域は、絶縁樹脂材料6、回路パターン7、及び
所望によりハンダレジストペースト8が延びており、一
方のホーローN2上の膜素子4と他方のホーローN2゛
上の膜素子4とが表面層の回路パターン7を介して互い
に接続されている。In addition, in FIG. 1, a large integrated circuit (LSI) is connected to the surface circuit pattern 7 of the multilayered wiring board.
9 and chip components 10 are placed on solder paste and reflow soldered to fix and mount them. Also,
On the other enamel layer 2, a thick film conductor (circuit pattern) 3 and a thick film resistor paste (resistance element) are placed in the same manner as above.
4 is printed and fired, and the polymer material (insulating resin material 6, circuit pattern 7) is polymerized. Enamel layer 2.2
An insulating resin material 6, a circuit pattern 7, and, if desired, a solder resist paste 8 extend in the area between the holes, and the film element 4 on one enamel N2 and the film element 4 on the other enamel N2 are on the surface. They are connected to each other via the circuit pattern 7 of the layer.
第2図に示した実施例は、前述のように、第1図に示し
た配線基板のホーローN2.2”間の領域21を折り曲
げたものである。このように、ホーロー基板では、厚膜
回路焼成後、基板を折り曲げることは困難であるが、ポ
リマー基板では可能であり、第2図の実施例が可能とな
る。なお、大型集積回路(LSI) 9やチップ部品l
O等に過度のストレスをかけることがなければ、これら
の部品の搭載の前後を問わず折り曲げ可能である。また
、ホーロー層2.2゛の大きさを所望に限定するなら基
材lの金属とガラス質のホーロー層2との膨張率差によ
り生ずる熱応力を許容範囲内に押さえることができる。As mentioned above, the embodiment shown in FIG. 2 is obtained by bending the region 21 between the enamel N2.2" of the wiring board shown in FIG. Although it is difficult to bend the substrate after circuit firing, it is possible with polymer substrates, making the embodiment shown in Figure 2 possible.
As long as excessive stress is not applied to the O, etc., these parts can be bent before or after they are mounted. Further, if the size of the enamel layer 2.2'' is limited to a desired value, the thermal stress caused by the difference in expansion coefficient between the metal of the base material 1 and the glassy enamel layer 2 can be suppressed within an allowable range.
このことにより、基材金属lとしてアルミニウム等の軽
金属を用いることが可能となる。This makes it possible to use a light metal such as aluminum as the base metal l.
第3図は、前述のように、金属基材1の両面に配線回路
を構成し、スルーホール31にて相互に接続した実施例
である。即ち、金属基材1の上面には、第1図の実施例
と同様の方法で多層化した回路を構成し、一方、金属基
材lの下面は、内層に抵抗素子等の厚膜素子を形成する
ことなく、絶縁樹脂材料6上に回路パターン7°を形成
し、大型集積回路(LSI) 9やチップ部品10等を
搭載したものである。上面のホーロー層2.2゛間の領
域には上下面を貫通するスルーホール31が形成され、
このスルーホール内の導体部分7”を介して上下の回路
パターン7.7”が互いに接続されている。FIG. 3 shows an embodiment in which wiring circuits are formed on both sides of the metal base material 1 and interconnected by through holes 31, as described above. That is, on the upper surface of the metal base material 1, a multilayered circuit is constructed in the same manner as in the embodiment shown in FIG. A circuit pattern 7° is formed on an insulating resin material 6 without forming a large scale integrated circuit (LSI) 9, a chip component 10, etc. thereon. A through hole 31 passing through the upper and lower surfaces is formed in a region between the enamel layers 2 and 2 on the upper surface.
The upper and lower circuit patterns 7.7'' are connected to each other via the conductor portion 7'' in this through hole.
以上に説明したように、本発明によれば、配線基板の内
層に信頼度の勝れた無機質の膜抵抗素子を構成すること
ができ、高密度の部品実装、配線パターンが可能となる
。As described above, according to the present invention, a highly reliable inorganic film resistance element can be formed in the inner layer of a wiring board, and high-density component mounting and wiring patterns are possible.
また、ホーロー基板を用いた場合、基板折り曲げ部をポ
リマー質で構成することで、配線が接続されたホーロー
の折り曲げ基板が可能となる。ホーロー基板の基材に軽
量のアルミニウム等を用いることが可能である。Furthermore, when a hollow substrate is used, by configuring the bending portion of the substrate with a polymer material, a bent hollow substrate to which wiring is connected becomes possible. It is possible to use lightweight aluminum or the like as the base material of the hollow substrate.
第1図は本発明の膜素子を内層した配線基板の第1実施
例の断面図、第2図は基板を折り曲げた本発明の配線基
板の第2実施例の断面図、第3図は基板の上下面をスル
ーホールで接続した本発明の配線基板の第3実施例の断
面図、第4図は第1図の実施例の配線基板の製造工程を
示す図、第5図及び第6図は従来の配線基板を説明する
ための断面図である。
1・・・金属基材、
2・・・ホーロー層、
3・・・回路パターン、
(厚膜導体ペースト)
4・・・厚膜抵抗素子、
5・・・ビアホール、
6・・・絶縁材料、
7・・・回路パターン、
(ポリマー専体ペースト)
・・・ハンダレジストパターン、
・・・大型集積回路(LSI)、
O・・・チップ部品、
l・・・折り曲げ部、
l・・・スルーホール。FIG. 1 is a cross-sectional view of a first embodiment of a wiring board having a film element of the present invention as an inner layer, FIG. 2 is a cross-sectional view of a second embodiment of a wiring board of the present invention in which the board is bent, and FIG. 3 is a board 4 is a cross-sectional view of a third embodiment of the wiring board of the present invention in which the upper and lower surfaces of the wiring board are connected by through holes, FIG. 4 is a diagram showing the manufacturing process of the wiring board of the embodiment of FIG. 1, and FIGS. 5 and 6 1 is a cross-sectional view for explaining a conventional wiring board. DESCRIPTION OF SYMBOLS 1... Metal base material, 2... Hollow layer, 3... Circuit pattern, (thick film conductor paste) 4... Thick film resistance element, 5... Via hole, 6... Insulating material, 7...Circuit pattern, (polymer-only paste)...Solder resist pattern,...Large integrated circuit (LSI), O...chip component, l...bending part, l...through hole .
Claims (2)
ーロー層上に無機質厚膜導体パターン(3)及び該パタ
ーンに接続する所望の厚膜回路素子(4)を印刷・焼成
してなる配線基板上に、絶縁樹脂層(6)を形成すると
共に該絶縁樹脂層を介してビアホール(5)等で所望に
より前記導体パターン(3)と該絶縁樹脂層の上に形成
した表面層配線パターン(7)とを接続したことを特徴
とする、膜素子を内層した配線基板。1. An enamel layer (2) is formed on a metal base material (1), and an inorganic thick film conductor pattern (3) and a desired thick film circuit element (4) connected to the pattern are printed and fired on the enamel layer. An insulating resin layer (6) is formed on the wiring board, and a surface layer wiring is formed on the conductor pattern (3) and the insulating resin layer as desired via a via hole (5) or the like via the insulating resin layer. A wiring board having a film element as an inner layer, characterized in that a pattern (7) is connected to the wiring board.
互いに間隔をあけて印刷・焼成し、ホーロー層上に無機
質厚膜回路(3,4)を形成し、区分された各ホーロー
層(2、2’)上の前記厚膜回路を覆うように絶縁樹脂
層(6)を形成し、絶縁樹脂層に形成した配線パターン
(7)により、区分された各ホーロー層上の前記厚膜回
路(3,4)間を相互に接続したことを特徴とする、膜
素子を内層した配線基板。2. Enamel layers (2, 2') are divided into metal base material (1), printed and fired at intervals, and an inorganic thick film circuit (3, 4) is formed on the enamel layer. An insulating resin layer (6) is formed to cover the thick film circuit on the layers (2, 2'), and the thickness on each divided enamel layer is A wiring board having a membrane element as an inner layer, characterized in that membrane circuits (3, 4) are interconnected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63156932A JP2699980B2 (en) | 1988-06-27 | 1988-06-27 | Wiring board with a film element inside |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63156932A JP2699980B2 (en) | 1988-06-27 | 1988-06-27 | Wiring board with a film element inside |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH027596A true JPH027596A (en) | 1990-01-11 |
| JP2699980B2 JP2699980B2 (en) | 1998-01-19 |
Family
ID=15638505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63156932A Expired - Lifetime JP2699980B2 (en) | 1988-06-27 | 1988-06-27 | Wiring board with a film element inside |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2699980B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1493187A4 (en) * | 2002-04-10 | 2008-03-19 | Heatron Inc | METHOD AND DEVICE FOR LIGHTING |
| US7791120B2 (en) | 2004-03-17 | 2010-09-07 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method thereof |
| CN109686721A (en) * | 2019-01-31 | 2019-04-26 | 中国电子科技集团公司第四十三研究所 | A kind of Thick film multilayer wire structures of low thermal resistance and preparation method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4628876B2 (en) * | 2005-06-07 | 2011-02-09 | 株式会社フジクラ | Light-emitting element mounting enamel substrate, light-emitting element module, lighting device, display device, and traffic signal device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55156477U (en) * | 1979-04-27 | 1980-11-11 | ||
| JPS5899855U (en) * | 1981-12-26 | 1983-07-07 | 株式会社フジクラ | enamel board |
| JPS5999787A (en) * | 1982-11-29 | 1984-06-08 | 富士通株式会社 | Thick film printed circuit board |
| JPS601858A (en) * | 1983-06-17 | 1985-01-08 | Sanyo Electric Co Ltd | Multilayer hybrid integrated circuit |
| JPS61181187A (en) * | 1985-02-07 | 1986-08-13 | 株式会社三協精機製作所 | Manufacture of thick film circuit |
| JPS6292354A (en) * | 1985-10-18 | 1987-04-27 | Hitachi Ltd | Hybrid ic |
-
1988
- 1988-06-27 JP JP63156932A patent/JP2699980B2/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55156477U (en) * | 1979-04-27 | 1980-11-11 | ||
| JPS5899855U (en) * | 1981-12-26 | 1983-07-07 | 株式会社フジクラ | enamel board |
| JPS5999787A (en) * | 1982-11-29 | 1984-06-08 | 富士通株式会社 | Thick film printed circuit board |
| JPS601858A (en) * | 1983-06-17 | 1985-01-08 | Sanyo Electric Co Ltd | Multilayer hybrid integrated circuit |
| JPS61181187A (en) * | 1985-02-07 | 1986-08-13 | 株式会社三協精機製作所 | Manufacture of thick film circuit |
| JPS6292354A (en) * | 1985-10-18 | 1987-04-27 | Hitachi Ltd | Hybrid ic |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1493187A4 (en) * | 2002-04-10 | 2008-03-19 | Heatron Inc | METHOD AND DEVICE FOR LIGHTING |
| US7791120B2 (en) | 2004-03-17 | 2010-09-07 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method thereof |
| CN109686721A (en) * | 2019-01-31 | 2019-04-26 | 中国电子科技集团公司第四十三研究所 | A kind of Thick film multilayer wire structures of low thermal resistance and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2699980B2 (en) | 1998-01-19 |
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