JPH027603A - Peak hold circuit - Google Patents

Abstract

PURPOSE:To reduce the time required for the circuit rising and trailing with simple constitution as a whole by applying on/off control to transistors(TRs) being components of a peak detection circuit through the use of an unsaturated TR circuit. CONSTITUTION:The title circuit consists of the peak detection circuit Q3 of emitter follower circuit configuration whose emitter is connected to a charge/ discharge capacitor 13 and of the unsaturated TR circuits 15-17, Q5-Q7. Then a base voltage VB1 of a TR Q3 driving the charge/discharge capacitor 13 is switched into a prescribed voltage VBE by using unsaturated TR circuits 15-17, Q5-Q7. Thus, the time required for the circuit rising and trailing is reduced with simple constitution as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a peak hold circuit, and is suitable for application to, for example, a magnetic disk drive.

B. Summary of the Invention The present invention provides a peak hold circuit for non-saturating C prior art.
The signal level of the servo signal is held for a predetermined period using a peak hold circuit as proposed in Japanese Patent No. 19685.

That is, as shown in FIG. 2, the magnetic disk l is divided into a servo area AR3 and a data area ARD at predetermined angular intervals, and the servo signals of frequencies fl and f2 are applied to the servo area AR5 with the track center TRC in between. S, □ and S! Areas ASB1 and ASB2 in which It is recorded are formed.

On the other hand, as shown in FIG.
, the reproduced signal 5II obtained from the magnetic head 4
F, A G C (autollIatic gain
control) frequency f1 and f2 via the circuit 5
The servo signals Sss+ and S are received by the bandpass filter circuits 6 and 7. Extract t.

The peak hold circuits 8 and 9 are composed of a peak detection circuit having an emitter follower circuit configuration in which an emitter is connected to a charge/discharge capacitor, and a transistor circuit that controls on/off a transistor connected to the charge/discharge capacitor in accordance with a control signal SC. , the magnetic head 4 is in the servo area AR3
During the scanning period, the peak-held servo signal S
The peak value of Sa+ and 8.2 is the output signal S. , and S
The signal is output to the tracking control circuit as OW.

As a result, in the tracking control circuit, servo signals S3□ and S are obtained during a period in which the magnetic head 4 scans the servo area AR3. Based on the servo signal S□,
and S! Even in the data area ARD where 0 cannot be obtained, tracking control is possible.

D Problems to be Solved by the Invention By the way, in this type of magnetic disk device, if the peak hold circuits 8 and 9 can be made to rise and fall in a short time in response to the control signal S, the magnetic disk capacity will be reduced accordingly. It is thought that the recording surface can be used effectively and the recording density can be increased.

However, in this type of peak hold circuit, the transistor circuit used for on/off control of the peak detection circuit operates in saturation, so there is a problem that the time required for rising and falling is long.

One way to solve this problem is to use a transistor circuit, and instead of controlling the transistor that drives the charging/discharging capacitor on/off, control the on/off by connecting the input end of the transistor circuit to a current source at a predetermined timing. There is a method using a peak hold circuit configured as described above.

However, this type of peak hold circuit has a problem in that the overall configuration is complicated, and it is still insufficient in practical use.

The present invention has been made in consideration of the above points, and aims to propose a peak hold circuit that has a simple overall configuration and can rise and fall in a short time.

E Means for Solving the Problem In order to solve this problem, in the present invention, a peak detection circuit Q3 having an emitter follower circuit configuration in which the emitter is connected to the charge/discharge capacitor 13, and a charge/discharge capacitor 1 are provided.
The transistor circuits 15, 16, 17, Q5, Q6, and Q7 of the non-saturation type are provided to switch the base voltage V□ of the transistor Q3 connected to the transistor Q3 to a predetermined voltage Vat.

The base voltage V□ of the transistor Q3 that drives the F action charging/discharging capacitor 13 is set to
6.17, Q5, Q6, and Q7 to switch to the predetermined voltage VSt, the time required for rising and falling can be shortened.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, lO indicates a peak hold circuit as a whole, and the servo signal S□ is transferred to an NPN transistor Ql.
give to

The transistor Ql constitutes a buffer circuit with an emitter follower circuit configuration together with the constant current source 11, and outputs its output signal via a PNP transistor Q2 which similarly constitutes a buffer circuit with an emitter follower circuit configuration together with the constant current source 12. It is applied to transistor Q3.

Thereby, the base voltage V□ of the transistor Q3 changes at a voltage equal to the signal level of the servo signal ssm.

Transistor Q3 charges and discharges the emitter of capacitor 13
is connected to form a peak detection circuit with an emitter follower circuit configuration, whereby the servo signal SS+
The peak value of S is obtained as the terminal voltage of the charging/discharging capacitor 13.

On the other hand, the diode-connected transistor Q5
and Q6 are connected to a constant current source 16 via a switch circuit 15 that operates on and off according to a control signal SC,
The other end is connected to the base and emitter of transistor Q7, respectively.

The transistor Q7 has an emitter grounded and a base grounded via a resistor 17.

Therefore, when the switch circuit 15 turns on, the transistor Q17 switches from the off state to the on state at an operating point determined by the current value of the constant current source 16 and the resistance value of the resistor 17, and as a result, the base voltage of the transistor Q7 increases. The pace emitter voltage is held at V□, and the collector voltage is held at the same potential as the base voltage.

Further, the transistor Q7 has its collector connected to the base of the transistor Q3, so that the base voltage V□ of the transistor Q3 changes from the collector voltage of the transistor Q7 (that is, the base emitter voltage of the transistor Voltage V mz
).

Therefore, in the transistor Q3, the switch circuit 15
During the period in which the servo signal ssm is turned on, the servo signal ssm is turned off, and the peak value of the servo signal ssm is maintained during this period.

At this time, the transistor Q7 is configured to operate in a non-saturated state at an operating point determined by the current value of the constant current source 16 and the resistance value of the resistor 17, so that the transistor that is controlled on and off as in the past operates in saturation. Compared to the case
The time required for rising and falling can be shortened.

Furthermore, in this embodiment, the time required for rise and fall can be shortened by simply adding three transistors Q5, Q6, and Q7, a constant current source 16, and a switch circuit 15 to the peak detection circuit. ,
As a result, a peak hold circuit having an overall simple configuration can be obtained.

Thus, the transistors Q5, Q6, and Q7, the constant current source 16, and the switch circuit 15 constitute a non-saturated transistor circuit that switches the base voltage V□ of the transistor Q3 connected to the charge/discharge capacitor 13 to a predetermined voltage V0.

In the above configuration, the servo signal ssm is provided to the transistor Q3 forming the peak detection circuit via two buffer circuits formed of the transistor Q1 and the constant current source 11 and the transistor Q2 and the constant current source 12.

As the switch circuit 15 turns on, the transistor Q
7 switches from the on state to the off state, the base voltage V□ of the transistor Q3 falls from the signal level of the servo signal SSS to the pace-emitter voltage V□ of the transistor Q7, thereby turning off the switch circuit 15. The peak value of the input servo signal So1 is detected during this period, and the detection result is held during the period during which the switch circuit 15 is turned on.

According to the above configuration, the emitter is connected to the charging/discharging capacitor 13.
By lowering the base voltage of the transistor Q3, which is connected to the peak detection circuit to form a peak detection circuit, to a predetermined voltage using a non-saturation type transistor circuit, the overall configuration is simple, and saturation is not achieved as in the conventional case. The time required for rising and falling can be shortened compared to the case of operation.

In the above-described embodiment, a case has been described in which the servo signal S is applied to the peak detection circuit through two buffer circuits, but the present invention is not limited to this. For example, the servo signal 33m is applied to the emitter follower circuit. It may be omitted if necessary, such as when output from the output circuit of the configuration.

Furthermore, in the above-described embodiment, a case has been described in which the peak hold of the servo signal 5sll is applied to a magnetic disk device, but the present invention is not limited to a magnetic disk device.
It can be widely applied to various electronic devices.

(Effects of the Invention As described above, according to the present invention, by using a non-saturation type transistor circuit to control on/off of the transistor that constitutes the peak detection circuit, the overall structure is simple. With this configuration, it is possible to obtain a peak hold circuit that requires short rise and fall times.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing a peak hold circuit according to an embodiment of the present invention, FIG. 2 is a route diagram showing a magnetic disk, and FIG.
The figure is a block diagram showing a magnetic disk device. 1...Magnetic disk, 8.9, lO...
・Peak hold circuit, 13...Charge/discharge capacitor, := 15...Switch circuit, Ql, Q
2, Q3, Q5, Q6, Ql...transistor. Peak hold circuit diagram 1

Claims (1)

[Scope of Claims] A peak detection circuit having an emitter follower circuit configuration in which an emitter is connected to a charging/discharging capacitor, and a non-saturating transistor circuit that switches the base voltage of a transistor connected to the charging/discharging capacitor to a predetermined voltage. A peak hold circuit that is characterized by the ability to