JPH027614A - Circuit configuration of logic filter - Google Patents

Abstract

PURPOSE:To obtain a circuit with a wide bit width, suitable for a digital real time signal and ease of large scale circuit integration by forming the circuit applying direct sequencing. CONSTITUTION:A nearby element extracting circuit 2 able to extract an optional nearby element of a noted element of an input signal, a sequencing circuit 4 receiving an output of the nearby element extracting circuit 2 and applying sequencing to the signal level, and a sequence selection output circuit 6 able to select and output a signal of an optional order in the output signal of the sequencing circuit 4 are provided to the filter circuit. Then the filter characteristic is varied by varying how to select the size, form and dimension of the nearby area, how to select a sequence selection signal or how to repeat the processing. Thus, the circuit is applied to a real time signal and excellent economy, high speed, small size and low power consumption are attained.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a logic filter circuit configuration that performs logical filtering on a signal that is sampled in -dimensional or multidimensional manner and arranged in -dimensional or multidimensional array. , especially the image 1m1lH
・Enter the logical filter circuit +f6 configuration that performs logical processing such as contraction.

(Summary of the Invention) In order to obtain an output for a specific element in an array that is an input signal, the present invention includes an element extraction circuit that extracts an element in the vicinity of that element, and an output of this element extraction circuit that is connected in parallel. By providing a ranking (=J) circuit that performs input and ranking according to the input level and a ranking selection output circuit that extracts signals of arbitrary ranking and outputs them, it is possible to effectively suppress irregular noise. There are circuit configurations of general-purpose logic filters that can perform removal, extraction of high-quality edge signals, dilation/contraction of figures, deformation of figures and waveforms, various band limitations, majority calculations, etc.

(Prior Art) Conventionally, this type of filter operation was introduced (this is by Prcston Jr., r3-FTLT).
ER8JIEEE Trans, on Vol.
85SP-31No, 4 Aug, 1983 48f
Peter D, Wendte et al.
t, at,, [5tack-Filtersj
IEEE Trans, on Vol, ^5SP-3
4N.

48 uu, 198G I+p898-911, and 16X circuit configuration, for example, R, G, 1
Iarber et al.

“VLSI Implementation of A
Fa3j Rank Order Filter
g ^Igorithn+J IC-8SSP
'85 TampaDp13ri6-1399
``and 'Quy B, Colenan R Real Time Ordinal Value Filter Using Reference Functional Comparison', US 1h Rev. TLsP45GO974''.

The methods proposed for configuring this type of filter circuit are as follows (in order):

(1) The input signal is converted into a large number of binary signals for each signal level by first threshold processing.

(2) Count the number of logical levels 1 included in the neighborhood abstraction region for all elements of all binarized signals for each signal level.

(3) The second fine-grained processing regarding the number of logic levels 1 in step 2) determines the binary output of each signal level.

(4) All outputs for the binarized signal for each signal level are increased or decreased, and the result of R Hiiragi is 1q.

(Problems that Komei tries to solve) Each of the steps (1) to 4) is a big brother in terms of circuit scale, and as it is, it will not be a circuit that can be applied to real-time signals. For example, in the case of a video signal of 8 bits], convert the input into a binary image of □256111, perform a logical operation on each binary image, and then add 256 sets of binary images to obtain the result. become. Therefore, R, G,
Harber et al. used analog circuits for the circuit that counts the number of logical level 1s in step (2) and the threshold processing circuit in step (3), and created a unique circuit configuration for step (4). By using this, circuits were constructed and LSI prototypes were produced, but the input signal was a maximum of 6 bits.

In addition, the circuit shown in the US Pat. ) can be performed compactly, but the input/output is analog, and such a circuit configuration is not suitable for LSI implementation.

In view of the above-mentioned points, an object of the present invention is to effectively solve the problems of the prior art, to configure a circuit that directly ranks bits without going through the above-mentioned steps (1) to 4), and to Wide range, adaptable to digital real-time signals,
The object of the present invention is to provide a logic filter circuit and structure that can be easily integrated into an LSI.

(Means for Solving and Overcoming the Problems) In order to achieve the above-mentioned object, the present invention provides a means for obtaining arbitrary neighboring elements for a certain element of an input signal which is arranged one-dimensionally or multi-dimensionally by sampling. A neighboring element extracting circuit that can extract 1, a ranking circuit that uses the output of this neighboring element extracting circuit as input, and ranks the signal level according to a ranking selection signal from among the outputs of the circuit. and a rank selection output circuit capable of selecting and outputting a signal of any rank, each of the circuits performs a series of processing, the configuration of the neighboring element extraction circuit, the magnitude of the rank selection signal, etc. and above-1
The present invention is characterized in that the filter characteristic i is changed by changing at least one of the number of repetitions of the heavy processing.

(Embodiments) Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a basic configuration diagram of a logical filter by Mitsuaki Ki. In the figure, the logical filter has a signal input terminal 1 for one or more sampled signals and selects one of the signals applied to this input terminal 1 to be used for the next processing. The neighboring element extracting circuit 2, which extracts and outputs the signal, and the output 3 of this neighboring element extracting circuit 2 are input in parallel, and the signals are ranked according to the signal level. The ranking of the outputs by rearranging them in ascending order (or descending order) is done by inputting the output signals 5 in parallel and applying them from the order selection signal input terminal 7. It is comprised of a rank selection output circuit 6 which can select a signal of an arbitrary rank from among the input signals in accordance with the received rank selection signal and output it from an output terminal 8.

Next, the operation of this logic 'noirter will be explained. The input signal applied to the signal input terminal 1 is a sampled signal, and may be a time-series-dimensional signal, an optically transmitted signal, or a calculated image, such as an audio signal or a television video signal. It may also be a parallel signal, such as a signal read from memory.

Further, the neighboring element extraction circuit 2 extracts the sampled time series -
By using various signal delay elements for dimensional signal input, while synchronizing with the sampling clock of the input signal,
This is a circuit for outputting in parallel the near 1'Pi key tree for the signal element of interest at the moment. On the other hand, in response to a parallel signal input such as an optically transmitted signal or a signal read out from an image memory, it is possible to output neighboring elements of the currently focused element and at the same time scan the focused element. They are also assumed to have the ability.

The ranking IJ circuit 4 is a circuit that ranks elements that are input in parallel according to their signal levels, that is, a "parallel sorter". The order of signal levels has a one-to-one correspondence.

The rank selection output circuit 6 is a so-called "selector" that connects one of the input terminals and the output terminal 8 according to the rank selection signal given from the rank selection signal input terminal 7. There is a one-to-one connection between the connections and the rank selection signal. Therefore, the order selection signal and the order of signal levels within the vicinity of the signal output from the output terminal 8 are as follows:
A one-to-one correspondence is possible. For example, if 1 is given to the rank selection signal input terminal 7, the signal with the highest signal level in the nearby area is output to the output terminal 8, and
By giving 2 to , the second largest signal can be output. At this time, (1) the conjunctive manner of the neighboring element extraction circuit 2, that is, the size and shape of the neighboring region; (2) the magnitude of the rank selection signal applied to the rank selection signal input terminal 7; and (3) the above-mentioned series of processing. By changing the number of repetitions (3), the characteristics of the logical filter can be changed, allowing more flexible processing than conventional logical filters.

Next, FIG. 2 shows a circuit configuration diagram of a two-dimensional logic filter for images, which is an embodiment of the present invention. In FIG. This logic filter is mainly composed of a neighboring element extraction circuit 2, a ranking input circuit 4, and a ranking selection output circuit 6. Among these, the neighboring element extraction circuit 2 receives the time-series signal input terminal 1, this input (a signal delayed by 1 line (or 1 frame) from signal a, and the signal delayed by 2 lines (or 2 frames) from the time-series signal input terminal 1,
In addition to the first delay element 21 for multiplying ij'3 by 1q and the outputs of two μ delay elements 21 in addition to the current input signal,
By ranking the signal levels of these three input signals, the largest signal H1, the medium signal M, the smallest signal L1, . : It consists of a three-point brisorter 22 that rearranges and outputs, and a second delay element 23 that delays each of the 3g outputs of the three-point brisorter 22 by one or two units. However, when the first delay element 21 is line rolling, the clock delay (horizontal one stroke Au extension) is - unit, and when it is frame rolling, the clock delay (one horizontal force roj Pixel delay) or line delay is set to the middle level.

The ranking shows that the circuit 4 has a total of nine output signals (
In other words, printed H and M.

L's 3 it! ] 211116 of the 3 sets) are merged and sorted in parallel, 611! An input parallel merge sort circuit 41 which obtains e(3,3) on the sorted neighboring elements of I, and the remaining set 311 of the six outputs of circuit/11 and the output of delay element 23 to this merge saw 1! It consists of a 7-digit (6.3) input parallel merge sort circuit 42 that connects the I signal in parallel.

Here, a group of m sorted house numbers and [1
Merge sort the groups in the same way as Zhou's sort, and create a new m+nl[! A parallel merge sort circuit that obtains l groups of sorted signals is referred to as an (m, n) input parallel merge sort circuit.

The rank selection output circuit 6 calculates (6, 3> from the width of the nine ranked output signals of the input parallel merge sort circuit 42,
According to the rank selection signal applied to the rank selection signal input terminal 7, a signal of an arbitrary rank is outputted to the output terminal 8.

Next, the operation of the logical filter 100 configured as described above will be explained.

The neighborhood element extraction circuit 2 consists of a first delay tree 21, a presorter 22, and a second delay element 23 for the im input manually to the input terminal 1, and in this embodiment, it extracts 3×3 neighborhood elements. Extract J0 Here, a line delay is used as the first logic element 21, and a clock delay (
(one pixel delay in the horizontal direction), for a TV image,
Processing can be performed as a horizontal-vertical two-dimensional image.

Also, a frame delay is used as the first delay element M21, and a clock delay (one pixel in the horizontal direction; predetermined) is used as the second delay.
For the TV image, use horizontal - frame (time)
Processing can be performed using two-dimensional images.

``In the evening, using a frame delay as the first delay element 21,
It is also possible to use a line delay as the second delay element 23 and process the television image as a vertical-frame (time) two-dimensional image.

The order is circuit 4, (3, 3) input parallel merge saw 1
- Consists of a circuit 41 and a (6, 3) input parallel merge sort circuit 42, which uses the Brisoak 22 to calculate 3g of 3g whose rankings have been changed in advance by δ for large (T1), medium (M), and small (L). Three sets of signals, a total of nine neighboring element signals, are merge-sorted in parallel on two sets, and the six ranked signals are increased by '+5'. After that, 1 navy blue 3fl left! Merge sort in parallel with + signal and output 9 ranked () as 1
Rir. According to such a method, the circuit size can be extremely reduced compared to directly ranking input signals of nine words, and LSI implementation is effective.

The rank selection output circuit 6 is a so-called selector, and according to the rank selection signal applied from the rank selection signal input terminal 7,
Signals of any order can be output to the output terminal 8.

Next, Fig. 3 shows a reference diagram for extracting neighboring elements of the logical filter of Fig. 2. The figure shows the shape of a 3×3 neighborhood area for the element (pixel) O of interest.

FIG. 4 shows a symbolic diagram of the logic filter of FIG. In the figure, reference numeral 9 denotes a logic filter main body, and parts having the same control functions as in FIG. 2 are given the same reference numerals.

FIG. 5 shows a series connection diagram of the logic filter of FIG. In the figure, there are a plurality of logical filter bodies 9-1, for example N logical filter bodies.
．． 9-2. ...9-N are connected in series, and each rank selection signal input terminal 7-1.7-2.・・・・・・7-N
It is possible to arbitrarily select and apply a ranking selection signal to be given to the output terminal 81 and output it from the output terminal 81.

FIG. 6 shows a reference diagram of the extraction size of neighboring elements.

Figure (A> is 2x2, Figure (B) is 3x3, Figure (C) is 4x
4. Figure (D) shows the case of 5x5, and Figure ([) shows the case of 7x7, which are examples of various sizes of the neighborhood region for the neighborhood element 0 of current interest.

FIG. 7 shows a reference diagram of the extraction form of various neighboring elements.

In the figure, an example of the shape of the neighborhood region for the neighborhood element O of current interest is shown for the case where the size is 3 x 3, but the way to take it is not limited to what is described here, but the size,
The shape, dimensions, etc. can be chosen arbitrarily.

Next, FIG. 8 shows a circuit configuration diagram of another embodiment C of a logic filter with an external merge input/output terminal according to the present invention.

In the figure, logic filter 20 with external merge input/output terminal
0 is mainly composed of a neighboring element extraction circuit 2, a ranking circuit 4, an input parallel merge saw 1/circuit 44, a group selection circuit 45, and a ranking selection output circuit 6. Among these, the input parallel merge sort circuit 44 receives nine outputs of the input parallel merge sort circuit 42 and three external merge inputs from external merge input terminals 43 (43-1, 43-2, 43-3). Perform a parallel merge saw 1.

In addition, the group selection circuit 45 includes the input parallel merge saw 1
・Among the outputs of the circuit 44, 3 from the one with the highest signal level
31 [! ] is input, and group selection No. 13 added to the group selection signal input terminal 46 selects the signal above the human signal level (η group 31 [
! ] or the 73 lower groupings of the signal level to the three external merge output terminals 47 (471, /I 7-2.47-
3) can be output.

The rank selection output circuit 6 inputs the output of the input parallel merge sort circuit 44 (f! Output to output terminal 8.

The basic operation of the logic filter 200 configured in this way is the same as that shown in FIG. 2, but the difference is that the external merge input terminal 43 (43-1, 43-2, 433) 47-1, 472, 47-3>,
A third manual parallel merge sort input 44, a group selection signal input terminal 46, and a group selection circuit 45 are added to expand the neighborhood area to be processed.

That is, when converting into an LSI based on a certain purpose of use, the size of the neighboring element obtained from the neighboring element extraction circuit 2 is fixed, but depending on the processing purpose, processing may be performed in a wider neighboring area. The need arises. On this occasion,
By using a plurality of LSI chips and providing an external merge input/output terminal 47 for inputting and outputting data from other chips, it is possible to expand and cover the neighboring area as necessary. In this example, only the largest three elements or the smallest three elements are taken as output among the elements in the expanded neighborhood region, and the performance of the logical filter is limited. However, this problem can be solved by increasing the number of external merge input/output terminals 47 as much as possible.

FIG. 9 shows a symbolic diagram of the logic filter of FIG. In the figure, 91 is a main body of a logic filter with external merge input/output, and parts having the same functions as those in FIG. 8 are given the same reference numerals. .

FIG. 10 shows a block diagram of the size expansion of the vicinity area of the logical filter of FIG. 8. In the figure, four logical filter bodies 91 with external merge input/output are used, and the size of the processed neighborhood region is expanded four times.

Next, FIG. 11 shows a circuit configuration diagram of a logical filter for spectrum conversion of a time-series signal, which is still another embodiment of the present invention. In the figure, this logical filter 300 mainly includes:
It consists of an input terminal 1 for a time-series signal such as an audio signal, a neighboring element extraction circuit 2, a ranking circuit 4, and a ranking selection output circuit 6. Among these, the neighboring element extraction circuit 2 delays the signal added to the input terminal 1 by 1 unit (such as the interval between 1 sample of a time series signal) and 2
It has a delay element 21 that obtains a unit delay and further an arbitrary unit delay. The ranking circuit 4 selects any input signal from among the input signals added to the output terminal of the delay element 21 and the input terminal 1 as input, and for the signal given to this input,
Ranking is performed according to the signal level and output. Also,
The ranking selection output circuit 6 inputs the output signals 5 ranked by the ranking circuit 4 and selects, from among these signals 5,
According to the rank selection signal added to the rank selection signal input terminal 7, an arbitrary signal is selected and outputted to the output terminal 8.

Such a logical filter 300 outputs, for example, the largest one from among the 1Δ numbers in a certain time range, or outputs the crowded one at the second gate, etc., for the sequence signal. , has the effect of transforming the waveform itself in order to selectively output or override it. Therefore, by selecting a relatively large ranking signal as the ranking selection signal, the waveform is modified while passing the low frequency portion, so that the sound quality can be intentionally changed.

(North Gate Effect) As explained above, the logic filter circuit according to the present invention includes a neighboring element extracting circuit that can extract any neighboring element of a target element with an input signal, and an output of this neighboring element extracting circuit as an input. A ranking circuit that ranks signal levels and a ranking selection output circuit that can select and output a signal of an arbitrary rank from among the output signals of the circuit are set up (-1). , the size and shape of the near-IVi region,
The filter characteristics can be changed by changing the dimension selection, the ranking selection signal, or the repeating process, so it is extremely effective in fields where only conventional linear filters have been used, for example as image filters. be.

It also removes noise without degrading the edge part of the waveform, extracts high-quality edge signals, produces motion signals in images, removes noise with a temporal component, deforms figures and waveforms, and expands and contracts images. , it is possible to apply it to majority voting processing, etc.

Furthermore, by converting the conventional logic filtering, which was mainly done in software, into hardware, it is possible to apply it to real-time signals, resulting in superior high-speed performance and performance, as well as smaller size and lower power consumption. Qin effects such as.

[Brief Description of the Drawings] Fig. 1 is a basic configuration diagram of a logical filter in the present invention;
Fig. 2 is a circuit configuration diagram of an image logic filter which is an example of the rAi of the present invention, Fig. 3 is a model number 4 for taking out the neighboring elements in Fig. 2, and Fig. 4 is a symbol diagram of the logic filter as well. ,
Fig. 5 is a series connection diagram, Fig. 6 is a reference drawing of the extraction size of neighboring elements, Fig. 7 is a model number diagram for extracting various neighboring elements, and Fig. 8 is a circuit of another embodiment of the present invention. Configuration diagram, No. 9
8 is a symbol diagram of the logic filter shown in FIG. 8, FIG. 10 is a diagram showing the enlarged size of the neighboring area shown in FIG. 8, and FIG. 11 is a circuit diagram of still another embodiment of the present invention. 1: Signal input terminal, 2: Neighboring element extraction circuit, 3: Neighboring element signal, 4: Ranking circuit, 5: Ranked signal, 6: Ranking selection output circuit, 7: Ranking selection signal input terminal,
8: Output terminal, 9: Logic filter body, 21 lines (
or frame) delay element, 22: 3-point resorter, 2
3: Clock (or line) delay element, 41: (
3,3) Input parallel merge sorter, 42: (6,3) Input parallel merge sorter, 43: External merge input terminal, 44
:(9,3) Input parallel merge sorter, 45 Nigel single selection circuit, 47: External merge output terminal, 100°200.
300: Ron Juri Philly.

Claims (1)

[Claims] 1) A neighboring element extracting circuit that can extract any neighboring element for a certain element of an input signal that is arranged in a one-dimensional or multidimensional array through sampling, and the output of this neighboring element extracting circuit is input, and the signal level is and a ranking selection output circuit capable of selecting and outputting a signal of an arbitrary ranking from among the output signals of the ranking circuit using a ranking selection signal; Logic characterized by performing a series of processes and changing filter characteristics by changing at least one of the configuration of the neighborhood element extraction circuit, the magnitude of the rank selection signal, and the number of times the series of processes is repeated. Filter circuit configuration.