JPH0277130A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To control a contact hole and a through hole in a tapered shape, and improve the coverage of wiring material by a method wherein non-uniform distribution of impurity with respect to the layer thickness is formed in an insulating film, an original form is previously patterned by dry etching, and then wet etching is executed. CONSTITUTION:An NSG insulating film 2 of 7000Angstrom thick is formed on a semiconductor substrate 1, phosphorus (P) as impurity 4 is diffused at 950 deg.C for 15min to perform doping. At this time, the impurity concentration is controlled so as to become lower from the surface of the insulating film 2 toward the film thickness direction. Next, a photoresist layer 3 is formed on the insulating film 2, and patterned; the original form of a contact hole is made by dry etching; the side surface of the contact hole is subjected to wet etching in which BHF is used as etching solution. As phosphorus concentration becomes lower, that is, the film depth approaches the interface of a lower layer, the etching rate becomes smaller, so that the contact hole having a desired shape can be easily formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a through hole and a contact hole for electrical connection.

(Prior Art) Conventionally, miniaturization of semiconductor devices has progressed only in the planar direction, but has not progressed comparatively in the vertical direction.

As a result, the aspect ratio of contact holes and through holes becomes large, and step coverage deteriorates during the next process of forming a layer of wiring material.As a result, wiring shorts occur and the yield of semiconductor devices decreases. lower. In order to improve this, a method has been considered to improve the step coverage of the wiring material by tapering the shape of contact holes and through holes.

(Problem to be Solved by the Invention) However, in the conventional method, it is not possible to etch contact holes and through holes into a tapered shape with good controllability, and as a result, short circuits may occur, which may reduce the yield of semiconductors. Ta.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional technical problems, an object of the present invention is to provide a method for manufacturing a semiconductor device having a desired tapered contact ball or through hole by etching with good controllability.

(Means for Solving the Problems) The present invention provides the following as means for solving the problems described above.
In a method for manufacturing a semiconductor device, there is a step of doping impurities to form an insulating film with a non-uniform impurity concentration distribution in the film thickness direction, and a process of dry etching and wet etching during patterning of the insulating film. The present invention provides a method for manufacturing a semiconductor device characterized by comprising the steps of:

According to the present invention, when etching the side surfaces of contact holes and through holes, the etching rate changes in proportion to the impurity concentration in the insulating film to increase the impurity concentration on the surface of the film, thereby increasing the impurity concentration in the underlying layer. By lowering the concentration closer to the interface, the etching shape can be made into a desired tapered shape.

Furthermore, according to the present invention, since the impurity profile can be easily controlled, it is also possible to control the desired taper shape extremely easily.

(Example) In a preferred embodiment of the present invention, in order to form a good tapered through hole or contact hole in an insulating film, an insulating film containing impurities is formed, dry etching is performed, and , perform wet etching.

In the present invention, a silicon oxide film or a silicon nitride film is suitably used as the insulating film.

Further, as the impurity, it is preferable to use a substance that forms an oxide having a different etching rate from silicon oxide, such as P, As, B, and the like. These are also more preferable because they do not deteriorate insulation properties.

Further, N may be used as an impurity for silicon oxide. In this case, silicon oxynitride (S) has a different etching rate than silicon oxide due to the N content.
This is to form ixoyNz). Further, in the case of a silicon nitride film, 0 is preferably used as the impurity.

It is also possible to contain a combination of a plurality of the above atoms, and in this case, the combination of B and P is
most preferred.

When the above-mentioned P, As, B, etc. are contained as impurities, the amount of side etching becomes large in areas where the impurity concentration is high, and becomes small in areas where the impurity concentration is low.

Further, when the silicon oxide film contains N, the amount of side etching becomes small in areas where the concentration of N is high, and the amount of side etching becomes large in areas where the concentration of N is low.

Furthermore, when the silicon nitride film contains 0, the amount of side etching becomes large in areas where the concentration of 0 is high.
Where the concentration of 0 is low, the amount of side etching becomes small.

Therefore, by changing the impurity concentration in the layer thickness direction, it is possible to obtain a desired tapered shape.

The most preferred embodiments of the present invention will be described below.
The present invention is not limited to the following examples.

(First Embodiment) FIGS. 1(a) to 1(d) are schematic diagrams showing the most characteristic formation of contact holes in the method of manufacturing a semiconductor device according to the present invention.

First, an NSG insulating film 2 is formed to a thickness of 700 degrees on an n-type or p-type semiconductor substrate 1 [FIG. 1(a)].

Next, phosphorus (P) is added to the NSG insulating film 2 as an impurity 4 so as not to affect the semiconductor substrate 1 as the underlying material.
Doping is carried out by diffusion at 950° C. for 15 minutes [Fig. 1(b)]. At this time, the impurity concentration is made to decrease from the surface of the insulating film 2 in the film thickness direction.

Next, a photoresist layer 3 is formed on the insulating film 2 and patterned. For example, in order to obtain a contact hole with a diameter of 1 tLm, the resist pattern has a diameter of 0.
After patterning the insulating film 2 to a thickness of 8 μm, a prototype of the contact hole is created by vertically etching the insulating film 2, for example, by dry etching such as reactive ion etching.
Figure (c)], at this time, the etching gas was CJa
and CHF3.

Next, wet etching is performed on the side surface of the contact hole using BHF as an etching solution.

The etching rate in BHF of an NSG film that is not doped with phosphorus (P) is 750 etching/min, but by diffusing phosphorus as an impurity, the phosphorus concentration is reduced to 1×10”atm/a.
The etching rate by BHF on the surface of the NSG film is 3000 people/min. Near the interface with l, the number is 750 people/+++in.

Therefore, from the above, B) By performing wet etching for 1 minute and 20 seconds using IF, the contact hole opening diameter on the insulating film surface becomes 1.8 μm, and the opening diameter at the interface with the substrate l becomes 1 μm, which is the desired value. A contact hole having a tapered shape can be easily formed [FIG. 1(d)].

The above also applies to through holes for electrical connection.

(Second Example) Next, a method for manufacturing a photoelectric conversion device that is suitably used as a method for manufacturing a semiconductor device according to the present invention will be specifically described using FIGS. 2(a) to 2(l).

First, as shown in FIG. 2(a), the impurity concentration I
On the back surface of the n-type silicon substrate 101 with an impurity concentration of lXl0''~
An n0 layer 102 for ohmic contact of l x 10 ``atm/ca+'' was formed by diffusion of P, As, or sb.Subsequently, on the n0 layer 102, a layer with a thickness of 3000~
7000 people's oxide film 103 (for example, SiO□ film)
It was formed by the VD method.

The oxide film 103 is called a back coat and is used to prevent the generation of impurity vapor when the substrate 101 is heat treated [FIG. 2(a)].

Next, the surface of the substrate 101 is etched for about 1.5 minutes at a temperature of 1000° C., HCl at 2 A/win, and Ht at 60 ρ/min.
iHaC1-(100%) with 1.2β/+afn, doping gas (OX diluted PI(,,20PPM>100
cc flow, growth temperature 1000℃, 120~l 80To
Under reduced pressure of rr, the n-epitaxial layer 104 (
Hereinafter, it will be referred to as n-layer 104. ) to form. At this time, the single crystal growth rate was 0.5 μm/win, and the thickness was 2~1O
μm, and the impurity concentration is I x 10” ~ 10”a
tm/cm3, preferably 10” to 10” ata+
/cm” [Fig. 2(b)].

Subsequently, an oxide film 108 for a pad with a thickness of 200 to 1000 is formed on the n- layer 104 by pyrogenic oxidation (H8+
O□), wet oxidation (Om + H, 0), steam oxidation (N m + HJ), or dry oxidation. Here, high-pressure oxidation at a temperature of 800 to 1000° C. is suitable for obtaining a good oxide film free of stacking defects and the like.

Next, nitride film (Si, ~4) of 1000-2000 people
121 is deposited by the LPCVD method or the P-CVD method [FIG. 2(C)].

In this example, the LPCVD method was used, and the deposition temperature was 77.
0 to 830°C, degree of vacuum 0.1 to 0.3 Torr, Si
H, C1g 20~30SCCM, NH, 70~l
Good results were obtained under the condition of 50 SCCM.

Next, the element isolation region 106 is etched by a dry etching method.
The portion of the nitride film 121 where the nitride film 121 is to be formed is selectively removed to form an opening 122 [FIG. 2(d)].

Next, using the nitride film 121 as a mask, impurity ions such as As and P are implanted into the n- region 104 using the ion implantation method, and the impurity concentration is set to lXl0'' to 5×10'' at+/
Cm".

Subsequently, it is electrically activated by heat treatment in a N2 atmosphere, and a selective oxidation method that takes advantage of the oxidation resistance of the nitride film is used.
A film with a thickness of 8,000 to
A too thick field oxide 111124 is selectively formed and the 00 region 123 is pushed to a predetermined depth.

In this way, the n region 12 is formed under the field oxide film 124.
An element isolation region 106 having a structure of 3 is formed [FIG.
)].

Next, the nitride film 121 is completely removed using heated phosphoric acid, the field oxide film 124 is left, and the oxide film 108 is removed.
was removed. After that, the gate insulating film 1 is again thermally oxidized.
An oxide film as No. 12 was formed to a thickness of 100 to 500 layers.

In this step, the back coat oxide film 103 is completely removed.

Subsequently, a resist 110 is applied, and the portion that will become the base region is selectively removed [FIG. 2(f) 1° Next, BF,
B1 ions generated as material gas, or BF2°
Inject ions into the wafer. This surface concentration is l x 10
16-5 X I O"cm-", preferably 1-20
X 10 "am-" and the ion implantation amount is 7X
10"~l x 10"cm-", preferably 1x1
0'a to IX10 "am-".

After the ions are implanted in this way, after removing the resist 11O, the impurities are implanted by thermal diffusion at 1000 to 1100°C in a N2 atmosphere.
m'' p base region 109 is formed to a predetermined depth [
Figure 2(g)].

Note that the depth of the p base region 109 is, for example, 0.6 to
The base region 109 can be formed by depositing BSG on the wafer and forming the base region 109 with a thickness of about 1 μm.
There is also a method in which the impurity B is diffused to a predetermined depth by thermal diffusion at 0 to 1200°C.

Next, the oxide film 112 in the portion where the emitter region will be formed is selectively removed, and then the polysilicon is (N 2+ 5I
It was deposited by CVD using H4) or (He+5iHn) gas. The deposition temperature at this time was 550-900°C, and the thickness was 4000-5000.

After that, As was ion-implanted into the polysilicon.
As the ion implantation conditions, the dose amount IEI5~5E l
6 atm/am”, acceleration 50-70KeV
Doped as.

After that, the polysilicon deposited in the opening where the oxide film was removed is heat treated to remove impurities such as As in the polysilicon.
The impurity concentration is 1×10 by diffusing into the p base region 109.
n9 emitter area 1 of “~1x102°atm/cm”
15 was formed.

Subsequently, the polysilicon was partially etched away using a photolithography process to form an emitter electrode section 116 and a gate electrode section 117 of the MOS transistor.
Figure 2 (h)].

Furthermore, after coating the photoresist, selectively remove only the resist where the source region of the MOS transistor is to be formed, and diffuse B to increase the impurity concentration I x 10 Is.
~I x 10 "atm/cm"(D") - A large area 11g was formed [FIG. 2(i)].

The process of providing an insulating film on the element substrate formed as described above and forming contact holes according to the present invention will be described in detail below.

The element substrate temperature is 400℃, SL! L is 1.042/m
in, 0□ to 0. IQ /min, N 2 l O
NSC was introduced under the conditions of j2/min, and by CVD method.
Film 120 was deposited on 5000-10000 people.

At this time, the NSG film 120 is 0 to 2000
Flow rate up to 0.2000 people is O, l A/m
By increasing the flow rate by in increments, an NSG film 120 with an impurity concentration varying in the film thickness direction was created [Fig. removed.

After that, 80SCCh of C and F were used as etching gas.
1, CHF5 was introduced at 20 SCCM, and dry etching was performed under a pressure of 60 Pa and an RF power of 2.1 kW.

Subsequently, after etching, wet etching using BHF is performed to form a tapered contact hole 126.
was formed [Fig. 2(k)].

Next, Al-3i was deposited to a thickness of 0.6 to 1 μm and patterned by a photo-etching process to form an electrode 129 and an Al-3L first wiring 125.

Again, similar to the formation of the NSG film 120 described above, an NSC film 128 whose impurity concentration changes in the film thickness direction is formed, and a through hole 127 is formed in the same manner as the formation of the contact hole 126 described above. 3i 2nd wiring 125°
was formed. [Figure 2 (β)].

Next, the basic operation of the photoelectric conversion device manufactured according to the present invention will be explained with reference to FIG. 2 (2).

P region 10 where light is the base of the bipolar transistor
9, charges corresponding to the amount of light are accumulated in the p region 109 (accumulation operation). The base potential changes due to the accumulated charges, and the potential change is transferred from the floating emitter electrode 115 through a capacitive load. By reading it out, you can obtain an electrical signal corresponding to the amount of incident light (readout operation)
.

Furthermore, in order to remove the charges accumulated in the p region 109,
The emitter 115 is grounded and a positive voltage pulse is applied to the gate 117 (refresh operation). By applying this positive voltage, p region 109 is forward biased with respect to n'' region 115, and the accumulated charge is removed.

Thereafter, the above-described storage, readout, and refresh operations are repeated.

In short, the photoelectric conversion method proposed here converts charges generated by incident light into the base p-region 10.
9, and the amount of accumulated charge controls the current flowing between the emitter and the collector (not shown). Therefore, the accumulated charges are amplified by the amplification function of each cell before being read out, making it possible to achieve high output, high sensitivity, and low noise.

The present invention is not limited to the above-mentioned embodiments, and for example, 5LON or the like can be used as the material of the glabella insulating film 2, and the 60 gas flow rate may be changed during film formation to By changing the oxygen concentration, it is also possible to form an insulating film having an oxygen concentration distribution in the film thickness direction that has the same effect as the impurity concentration distribution described above. For example, by plasma CVD method, 5
Under the conditions of iH4170SCCM, NH-600SCCM, applied RF current of 2, OA, and temperature of 300°C, 5iON is generated in the SiN film and the film thickness is The insulating film can have an oxygen concentration distribution that changes in the direction.

Furthermore, SF or the like can be used as the dry etching gas, and BHF solution or the like can be used as the wet etching solution.

(Effects of the Invention) The present invention provides a non-uniform distribution of impurities in the layer thickness direction in an insulating film, and performs wet etching after patterning the original pattern by dry etching, thereby forming contact holes and through holes. The tapered shape can be easily controlled and the step coverage of the wiring material can be improved. As a result, short circuits in the wiring can be prevented and the yield and reliability of semiconductor devices can be improved.

Furthermore, since the present invention uses both dry etching and wet etching, compared to the conventional method of forming through holes and contact holes using only dry etching, dry etching is terminated earlier when the end point of etching is detected, and wet etching is then performed. , you can expect a good finish. Therefore, the overetching time during dry etching can be shortened, damage to the underlying layer due to dry etching can be reduced, and reliability can be improved.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are schematic process diagrams showing an embodiment of a method for manufacturing a semiconductor device according to the present invention. FIGS. 2(a) to 2(I2) are schematic process diagrams showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. 1... Semiconductor substrate 2... Insulating film 3... Resist layer 4... Impurity 101... (n-type silicon) substrate 102... n0 layer 103... Oxide film (back coat) 104...N- layer 106...Element isolation region 108...Pad oxide film 109...P base region 110...Resist 112...Gate insulating film 115...N9 emitter region (emitter electrode) 116
...Emitter electrode part 117...Gate electrode part 118...Source region 120...NSC film 121...Nitride film 122...Opening part 123...N'' layer (region) 124... ...Field oxide film 125...A9-3i first wiring 125''...Al2-Si second wiring 126...Contact hole 127...Through hole 12B...NSC film 129...Al1- 5i Electrode Representative Patent Attorney Jo Taira Yamashita Figure 1 0.8 layer m Figure 2 Figure 2 Figure 2

Claims (1)

[Claims] A method for manufacturing a semiconductor device includes a step of doping impurities to form an insulating film having a non-uniform impurity concentration distribution in the thickness direction of the film, and a step of drying during patterning of the insulating film. 1. A method for manufacturing a semiconductor device, comprising a step of using etching and wet etching in combination.