JPH02772U - - Google Patents
Info
- Publication number
- JPH02772U JPH02772U JP7766088U JP7766088U JPH02772U JP H02772 U JPH02772 U JP H02772U JP 7766088 U JP7766088 U JP 7766088U JP 7766088 U JP7766088 U JP 7766088U JP H02772 U JPH02772 U JP H02772U
- Authority
- JP
- Japan
- Prior art keywords
- hole
- wall
- stacked
- exposed
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Description
第１図は本考案の一実施例としてのセラミツク
多層基板の断面図、第２図は前記セラミツク多層
基板の平面図、第３図ａ〜ｄはそれぞれセラミツ
ク多層基板の製造工程を説明するための図で、図
ａ及びｂはグリーンシートからカツトされ、かつ
配線パターンが形成されたセラミツク基板の平面
図、図ｃ及びｄは複数枚が積層された状態を示す
セラミツク基板の断面図、第４図はスルーホール
内壁に設けられた抵抗膜を切削する状態を説明す
る平面図である。
１……セラミツク多層基板、１ａ〜１ｄ……セ
ラミツク基板、２ａ，２ｂ……配線パターン、３
……スルーホール、４……抵抗膜。
FIG. 1 is a sectional view of a ceramic multilayer substrate as an embodiment of the present invention, FIG. 2 is a plan view of the ceramic multilayer substrate, and FIGS. 3a to 3d are diagrams for explaining the manufacturing process of the ceramic multilayer substrate. In the figures, figures a and b are plan views of a ceramic substrate cut from a green sheet and on which a wiring pattern is formed, figures c and d are cross-sectional views of the ceramic substrate showing a state in which a plurality of ceramic substrates are laminated, and Fig. 4 FIG. 2 is a plan view illustrating a state in which a resistive film provided on the inner wall of a through hole is cut. 1... Ceramic multilayer board, 1a to 1d... Ceramic substrate, 2a, 2b... Wiring pattern, 3
...Through hole, 4...Resistive film.
Claims (1)
板複数枚が積層され、積層されたセラミツク基板
を貫通してスルーホールが設けられ、該スルーホ
ール内壁に前記配線パターンの一部が露出し、か
つ、これらの露出した各基板間の配線パターンを
つなぐ状態でスルーホール内壁に抵抗膜が形成さ
れていることを特徴とするセラミツク多層基板。 A plurality of thin ceramic substrates on which wiring patterns are formed are stacked, a through hole is provided through the stacked ceramic substrates, and a part of the wiring pattern is exposed on the inner wall of the through hole. A ceramic multilayer board characterized in that a resistive film is formed on the inner wall of the through hole to connect the exposed wiring patterns between each board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7766088U JPH02772U (en) | 1988-06-10 | 1988-06-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7766088U JPH02772U (en) | 1988-06-10 | 1988-06-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02772U true JPH02772U (en) | 1990-01-05 |
Family
ID=31302633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7766088U Pending JPH02772U (en) | 1988-06-10 | 1988-06-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02772U (en) |
-
1988
- 1988-06-10 JP JP7766088U patent/JPH02772U/ja active Pending