JPH0277938A - Lsi logic circuit device - Google Patents

Abstract

PURPOSE:To prevent an output signal for the normal working from affecting other logic circuit devices which are performing no scan action by providing an output inhibiting gate to invalidate all output signals for the normal working during a scan action. CONSTITUTION:When a scan action is instructed by the scan control signal supplied from a scan control signal input terminal 1, a scan-in signal is supplied from a scan-in signal input terminal 2. A memory element 3 sends the memory data to another element 3 set at the stage after a scan bus and at the same time stores the input data. The memory data on all elements 3 are successively outputted from a scan-out signal output terminal 4. In this case, an output inhibiting gate 5 is validated by the scan control signal supplied from the terminal 1 during a scan action. Thus the output signal supplied from a signal output terminal 6 for the normal working is invalidated. In such a way, other logic circuit devices having no scan action are never affected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an LSI logic circuit device constituting a data processing device, and particularly relates to an LSI logic circuit device having a scan function.

[Prior Art] Conventionally, the scan function in an LSI logic circuit device is
This is a well-known technique that facilitates the diagnosis of a data processing device consisting of a single SI logic circuit device or a plurality of LSI logic circuit devices, and is also used as a means for collecting fault information of the data processing device.

FIG. 2 is a schematic configuration diagram showing a conventional LSI logic circuit device. In FIG. 3 selects the input data supplied from the scan path in the case of scan operation, or the input data supplied from the combinational circuit for normal operation in the case of normal operation. 4 is a scan-out signal output terminal for outputting data of the memory element 3 that is sequentially read from the scan path during a scan operation, and 6 is a signal output terminal for normal operation.

Next, the operation of the above conventional LSI logic circuit device will be explained. When a scan operation is instructed by a scan control signal supplied from scan control signal input terminal 1, a scan-in signal is supplied from scan-in signal input terminal 2. Further, the storage element 3 sends the stored data to the storage element 3 at the next stage of the scan path, and also stores the data input from the scan path. In this way, the data stored in all the storage elements 3 is sequentially outputted from the scan-out signal output terminal 4. During this time, the scan path configured by connecting all the memory elements 3 in series works as a shift register, so the data stored in the memory elements 3 changes with the shift operation, and as a result, from the signal output terminal 6 for normal operation. The output signal of will also change.

On the other hand, when the scan control signal supplied from the scan control signal input terminal 1 instructs normal operation, the memory element 3 works to input data supplied from the combinational circuit for normal operation, and this LSI logic circuit device implements a first-order logical function.

[Problems to be Solved by the Invention] Since the above conventional LSI logic circuit device is configured as described above, during the scan operation, the signal output terminal 6 for normal operation changes as the contents of the storage element 3 change. Since the output signal changes, if the signal output terminal 6 that outputs this output signal is connected to a second logic circuit device configured to perform normal operation even during the scanning operation of the present LSI logic circuit device. However, there was a problem in that the operation of the second logic circuit device was not guaranteed.

This invention was made to solve the above-mentioned problems, and provides an LSI in which meaningless changes in normal operation output signals caused by scan operations do not affect the operation of other logic circuit devices. The purpose is to obtain a logic circuit device.

[Means for Solving the Problems] An LSI logic circuit device according to the present invention includes an output inhibit gate that is enabled during a scan operation, and this output inhibit gate inhibits all output signals for normal operation during the scan operation. This is to disable it.

[Operation] The LSI logic circuit device of the present invention includes an output inhibit gate that is enabled during a scan operation, so that the output inhibit gate disables all output signals for normal operation during the scan operation. to work.

[Embodiment 1] FIG. 1 is a schematic configuration diagram showing an LSI logic circuit device according to an embodiment of the present invention. In FIG. 0, 1 is a scan control signal input terminal for switching between scan operation and normal operation, and 2 is a scan control signal input terminal A scan-in signal input terminal for supplying data to the scan path during scan operation, 3 is a combination for input data supplied from the scan path during scan operation, and for normal operation during normal operation. 4 is a memory element for selectively storing input data supplied from the circuit; 4 is a scan out signal output terminal for outputting the data of memory element 3 that is sequentially read out from the scan path during a scan operation; 5 is a scan out signal output terminal; The output inhibit gate is enabled during the scan operation, and 6 is a signal output terminal for normal operation.

Next, the operation of the LSI logic circuit device according to the embodiment of the present invention will be explained. In the operation of the LSI logic circuit device according to the present invention, in the case of normal operation, the output inhibit gate 5 is disabled, so that the operation is exactly the same as that of the above-mentioned conventional example. Therefore, a description of its operation will be omitted.

On the other hand, during the scan operation, the scan control signal supplied from the scan control signal input terminal 1 causes the output prohibition gate 5 to
is controlled to be valid, the output signal output from the signal output terminal 6 for normal operation is invalidated, and therefore the output signal does not change with the scan operation.

In the above embodiment, a case has been described in which a dedicated output inhibit gate 5 is provided, but instead of this, a logic gate included in a combinational circuit may be used to perform the same function.

[Effects of the Invention] As described above, according to the LSI logic circuit device of the present invention, the LSI logic circuit device includes an output inhibit gate that is enabled during a scan operation,
This output inhibit gate is configured to disable all output signals for normal operation during scan operation.
This has the excellent effect of eliminating the influence on other logic circuit devices that are not performing scan operations.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an LSI logic circuit device according to an embodiment of the present invention, and FIG. 2 is a schematic configuration diagram showing a conventional LSI logic circuit device. In the figure, 1...scan control signal input terminal, 2...
...Scan-in signal input terminal, 3...Storage element,
4...Scan out signal output terminal, 5...Output inhibit gate, 6...Signal output terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A plurality of memory elements, a scan path configured by connecting these memory elements in series, a scan control signal input terminal for switching between a shift operation and normal operation using this scan path, and a scan path to the scan path. A scan-in signal input terminal for inputting data, a scan-out signal output terminal for outputting data from the above scan path, a signal output terminal for normal operation, and all normal operations during scan operation. L characterized in that it is equipped with an output inhibit gate that operates to invalidate the output signal for
SI logic circuit device.