JPH0277987U - - Google Patents
Info
- Publication number
- JPH0277987U JPH0277987U JP1597589U JP1597589U JPH0277987U JP H0277987 U JPH0277987 U JP H0277987U JP 1597589 U JP1597589 U JP 1597589U JP 1597589 U JP1597589 U JP 1597589U JP H0277987 U JPH0277987 U JP H0277987U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- read
- circuit
- data
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
Description
図は何れも本考案の一実施例を示し、第１図は
本実施例の動作原理説明図、第２図は回路ブロツ
ク図、第３図は信号切換回路の回路ブロツク図を
、それぞれ示す。
２，３，４，５……フイールドメモリ、７……
アドレス発生回路、１……ＡＤ変換回路、９……
ＤＡ変換回路。
Each of the figures shows an embodiment of the present invention; FIG. 1 is an explanatory diagram of the operating principle of this embodiment, FIG. 2 is a circuit block diagram, and FIG. 3 is a circuit block diagram of a signal switching circuit. 2, 3, 4, 5...field memory, 7...
Address generation circuit, 1...AD conversion circuit, 9...
DA conversion circuit.
Claims (1)
周期で右目情報と左目情報に交互に切換えて成る
立体映像信号を形成導出する映像信号源と、 前記立体映像信号をカラーサブキヤリア周波数
の逓倍の周波数でデイジタル化してＡＤ変換デー
タを形成導出するＡＤ変換回路と、 前記ＡＤ変換データを記憶するフレームメモリ
と、 前記ＡＤ変換データを順次前記フレームメモリ
に記憶せしめる書込みアドレスと、前記フレーム
メモリに対する１回目の読出終端と２回目の読出
始端を合わせて１ライン分省略してデータをフレ
ーム周波数の２倍の速度で読出す読出アドレスと
を、それぞれ導出するアドレス発生回路と、 前記フレームメモリの読出データをアナログ化
して再合成立体映像信号を形成導出するＤＡ変換
回路とを 配することを特徴とする立体映像信号再合成回
路。[Claims for Utility Model Registration] A video signal source for forming and deriving a stereoscopic video signal by alternately switching the video information of a standard television signal into right-eye information and left-eye information in a field period, and converting the stereoscopic video signal into a color subcarrier. An AD conversion circuit that forms and derives AD conversion data by digitizing it at a frequency that is multiplied by a frequency; a frame memory that stores the AD conversion data; a write address that sequentially stores the AD conversion data in the frame memory; an address generation circuit that derives a read address for reading data at twice the frame frequency by omitting one line in total from the end of the first read and the start of the second read to the memory; and the frame memory. A 3D video signal resynthesis circuit characterized in that the 3D video signal resynthesis circuit is provided with a DA conversion circuit for converting read data into analog to form and derive a resynthesized 3D video signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1597589U JPH0633741Y2 (en) | 1988-08-30 | 1989-02-14 | 3D video signal re-synthesis circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63-113609 | 1988-08-30 | ||
| JP11360988 | 1988-08-30 | ||
| JP1597589U JPH0633741Y2 (en) | 1988-08-30 | 1989-02-14 | 3D video signal re-synthesis circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0277987U true JPH0277987U (en) | 1990-06-14 |
| JPH0633741Y2 JPH0633741Y2 (en) | 1994-08-31 |
Family
ID=31717331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1597589U Expired - Lifetime JPH0633741Y2 (en) | 1988-08-30 | 1989-02-14 | 3D video signal re-synthesis circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0633741Y2 (en) |
-
1989
- 1989-02-14 JP JP1597589U patent/JPH0633741Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0633741Y2 (en) | 1994-08-31 |
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