JPH027896A - Pulse phase-switching circuit - Google Patents

Abstract

PURPOSE:To ensure the switching of phase inversion and to perform normal and reverse rotations certainly by delaying the counter output with a delayer. CONSTITUTION:A counter 10 counts a clock CK, from which its divided output is generated and it is used for driving pulses of a pulse motor. With a delayer 20 the counter output is delayed and inputted into a pulse inverter 30. When a pulse signal T is inputted into the phase inverter 30, it presets or resets the counter 10 and performs the phase inversion of the counter output. Since the pulse signal T directly acts on the counter 10, the pulse inversion of the counter 10 can surely be performed as soon as the pulse signal is inputted.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a pulse phase switching circuit, an object of the present invention is to provide a phase switching circuit capable of inverting the phase of a counter using a pulse control signal, and to count clocks and divide the frequency thereof. a counter that produces an output;
A control pulse for phase switching is inputted, and the output of the counter is inputted through a delay device. It is configured to include a switch for presetting or clearing.

[Industrial application field]

The present invention relates to a pulse phase switching circuit used for forward and reverse rotation of a stepping motor.

In recent years, the number of mechatronic systems such as quartz analog clocks has increased, and stepping motors have come into widespread use. As is well known, the speed of a stepping motor is determined by the frequency of the pulses applied to the stepping motor, and the rotation direction is determined by reversing the phase of the pulses, for example, A phase, B phase, C phase, A phase, B phase, C phase, etc.・
...The ones that were excited in the order of C phase, B phase, A phase, C
Phase, B phase, A phase, etc. are inverted by excitation in this order.

The present invention relates to a phase switching circuit for reversing the pulse phase.

[Conventional technology]

Conventionally, when inverting the phase of a pulse signal, the simplest method is to use an exclusive OR (EOR, ENOR) circuit. Since the truth table of EOR is as shown in Table 1, by setting one input to H, the inversion of the other input can be obtained at the output terminal.

When one input is set to L, the other input appears directly at the output terminal.

Table 1 However, in this method, the phase inversion control signal (- input A or B) needs to be maintained at H (for EOR) or L (for ENOR) during phase inversion.

To invert the phase of the exclusive OR circuit even with a pulse signal, it is possible to use a flip-flop that operates to toggle. An example of this is shown in FIG. 7, where FF is the flip-flop. Every time the control signal pulse T is input, the Q output of this flip-flop, so the input A changes to H, L, H, .
..., so if the input of pulse T is stopped when it is H, the output Y of EOR becomes B.

(Problem to be solved by the invention) When exclusive OR is used for phase inversion as described above, the inversion control signal needs to be a level rather than a pulse.A T-FF that operates toggles is added to convert the inversion control signal. If it is added to this, a pulse can be used, but in this case it is necessary to know the output state of the T-FF by some means.In other words, the Q output of the flip-flop T-FF is H and EOR
Since the output of Q is inverted and passed, it is necessary to know whether the Q output is H or L. Of course, this inversion control method cannot be used unless an EOR gate is used.

A counter is often used to generate drive pulses for a pulse motor, and reversal control means that directly acts on the counter is desirable for reversing the rotational direction of the pulse motor.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase switching circuit capable of inverting the phase of a counter using a pulse control signal.

(Means for Solving the Problems) As shown in FIG. 1, the present invention provides a counter 10 with a delay device 20 and a switch 30.

The counter 10 is divided by 172 or 1/2 by continuously connecting one flip-flop or n flip-flops.
fi frequency division counter.

The delay device 20 delays the counter output and transmits it to the switch 30.

The switch 30 receives the pulse signal T for inversion control and inverts the phase of the output of the counter 10.

[Effect]

In this circuit, a counter 10 counts the clock CK and produces a frequency-divided output thereof, which is used for pulse motor drive pulses and the like. In addition, the delay device 20 causes a delay in the switching device 3.
Enter 0. When the pulse signal T is input, the switch 30 presets or resets the counter 10 and inverts the phase of the counter output.

〔Example〕

FIG. 2 shows an embodiment of the present invention. In this example, counter 10
is a flip-flop FF that operates toggle.

The delay device 20 is composed of a D-FF flip-flop FFz. Further, the switching device 30 is composed of Nant gates G, , G,.

To explain the operation with reference to the waveform diagram in FIG. 3, the flip-flop FF has its own Q
Take the output to the data terminal and invert the Q output. The Q output of this FF is the output of this circuit, and is used for driving a pulse motor.

The output frequency is 1/2 of the clock CK.

Flip-flop FF2 is the Q of flip-flop FF1
Capture the output at the falling edge of clock CKz.

Therefore, the Q output a becomes as shown in the figure. Output a enters a Nandt gate G+, the other input of which is the inversion control pulse T. The input of the Nant gate G2 is the pulse T
is the output of the Nandt gate Gr. Nando game) G
The output of + is also input to the preset terminal PR of flip-flop FF, and the output of Nant gate G2 is fii
Input to the clear terminal CLR of F.

Therefore, as shown in FIG. 3, when the control pulse T is input when the output a is H, the output of the Nandt gate G1 becomes L,
FF, and set its Q output to H (a-H
Then, Q=L). Since the L output of G is input to the Nant gate Gz, the output is H and does not clear FF. Further, when the Q output of the flip-flop FF becomes H as preset by the output of the Nant gate GI, the flip-flop F F z takes this in at the falling edge of the clock CK, and therefore the Q output a becomes L. Therefore, the output of the Nant's gate G becomes H, and since the control pulse T has disappeared at this point, the output of the Nand's gate G2 remains at H, so that G t and G z do not act on FF1. Flip flop FF.

continues the toggle operation based on the clock CK, and outputs a rectangular wave having an opposite phase (reverse order) to that before the control pulse T was input, as shown in the figure.

When the output a is at the L level (therefore, the Q output of the FF is at the H level), when the inversion control pulse T is input, the Nant gate G
Since the output of I is H, there is no need to preset the FF, but instead the output of Nant gate G2 becomes L and the FF is
, and sets the Q output to L to invert the output rectangular wave.

In either case, when the control pulse T is input, the phase of the output is inverted.

The flip-flop FF provides a delay. That is, if the Q output of FF except FF is given to the Nant gate G1, when Q=H and T becomes H, the output of Gl becomes L.
, preset the FF, and set it to Q-H (
The phase is reversed, but since Q=L at this time, the GI output becomes H, and the preset is stopped. In other words, the pulse width of the preset pulse becomes extremely short, and the preset (phase inversion) operation becomes uncertain or cannot be performed. If there is a delay, the pulse width of the preset pulse can be secured and reliable preset (phase inversion) can be performed.

Clocks CKz and CK are independent of each other,
It doesn't need to be in sync. The only thing that needs to happen is that the clock CK2 has a sufficiently shorter period than the clock CK.

The forward and reverse rotation of a pulse motor is well known, and an example of a four-phase pulse motor is shown in FIG. (2)～(
5) indicates the A, B, C, and D phase excitation voltages. If H level is energized and L level is de-energized, excitation is A, B, B, and C.
Take 9C, D and A, A and B.

. . . are carried out in two phases at a time, and the motor rotates in the normal direction.

(6) to (9), reverse the excitation order to B, A, and A.
bird.

When D and C1C and B, B and A, etc., the motor reverses. To reverse a fully normal rotation at time L0, for example, it is sufficient to continue the start of (6) A phase to the end of (2) A phase, and this is the phase reversal seen in the output (5) in Figure 3. It is a waveform.

FIG. 5 shows a drive pulse generation circuit for a four-phase pulse motor. φ, to φ4 are the driving pulses, and φ,=φ3. φ2=φ
4. φ1 and φ2 have a phase shift of π/2. F
F, -FF is a flip-flop, and FF receives the clock CK, performs a toggle operation, and converts 1/1 of the clock CK.
Generates a square wave with a frequency of 2. The Q output of FF is FF
, and the Q output of FF is input as a clock of FF s, and FF3 performs a toggle operation to generate the drive pulse φ1. This is inverted by the inverter 11 to obtain the drive pulse φ3. flip flop FF
, uses the Q output of FF as data, takes this in with the Q output of FF, generates a drive pulse φ2, and inverts this with an inverter I2 to obtain a drive pulse φ4.

Flip-flop FF, , Nant gate G, G2 is the second
This corresponds to that shown in the figure, and switches the output rectangular wave phase.

FF, and Nantgate G's, Ga and FF
& and Nant Gate C;5. G has the same functions as FF, Nant Gate G+, and Gz.

As shown in FIG. 6, the four-phase pulse motor of this example is excited in two phases, φ2φ3. φ3φ4. φ4φ1゜φ1 φ2. φ
2φ (the first to fourth phase windings of the motor are also indicated by φ1 to φ4), when the inversion control signal T is input, the flip-flop FF3 is inverted, and then the clock CK, When input, it is further inverted. By setting the L level during this period, the excitation direction is reversed after reversal control, and the motor rotates in reverse.

The presetting and clearing operations in which the counter 10 includes n flip-flops may be performed on the final stage flip-flops of the counter, or may be performed on all flip-flops.

When the counter is composed of n flip-flops, various frequency-divided outputs can be obtained, so this counter can be used not only for driving a pulse motor but also as a driving pulse source for various parts of mechatronics.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to invert the phase of an output rectangular wave using a pulse signal, and there is an advantage that the phase inversion can be reliably carried out immediately upon inputting the pulse signal. .

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the invention, Fig. 3 is a waveform diagram for explaining the operation of Fig. 2, and Fig. 4 is an explanation of forward and reverse rotation of the pulse motor. 5 is a drive pulse generation circuit diagram of a four-phase pulse motor, FIG. 6 is a waveform diagram for explaining the operation of FIG. 5, and FIG. 7 is an explanatory diagram of an example of a phase inversion circuit. In FIG. 1, 10 is a counter, 20 is a delay device, 30 is a switch, CK is a clock, and T is a phase inversion control pulse. IT diagram Circuit i71 showing an embodiment of the present invention Figure 2 +41 Y Waveform diagram for explaining the operation of Figure 2 Figure 3 (t) CLK Diagram for explaining forward and reverse rotation of the pulse motor Figure 4 Figure 6

Claims (1)

[Claims] 1. A counter (10) that counts a clock (CK) and generates a frequency-divided output, and a control pulse (T) for phase switching is input, and the output of the counter is input through a delay device (20) to perform the control. A pulse phase switching circuit comprising a switch (30) that presets or clears the counter according to the H level or L level of the counter output input through the delay device when a pulse is input.