JPH0281060U - - Google Patents
Info
- Publication number
- JPH0281060U JPH0281060U JP16002088U JP16002088U JPH0281060U JP H0281060 U JPH0281060 U JP H0281060U JP 16002088 U JP16002088 U JP 16002088U JP 16002088 U JP16002088 U JP 16002088U JP H0281060 U JPH0281060 U JP H0281060U
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- oxide film
- semiconductor device
- contact
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案を適用したＩＣチツプの模式的
な部分平面図、第２図は第１図のＡ―Ａ′断面図
、第３図は第１図のＢ―Ｂ′断面図、第４図は第
１図のＣ―Ｃ′断面図、第５図は、従来技術の断
面図である。
１……集積回路チツプ、２……素子領域、２′
……素子領域近傍域、３……導電層（最低電位）
、４……最低電位電源パツド、４′……パツド、
５……コンタクト部、５′……コンタクトホール
、６……１層の導電層（最低電位）、７，８，９
……スルーホール、１０……半導体基板、１１…
…素子分離酸化膜、１２，１４，１６……導電層
（配線）、１７，１８，１９……導電層（パツド
コンタクト）。
FIG. 1 is a schematic partial plan view of an IC chip to which the present invention is applied, FIG. 2 is a sectional view taken along line AA' in FIG. FIG. 4 is a sectional view taken along line CC' in FIG. 1, and FIG. 5 is a sectional view of the prior art. 1... Integrated circuit chip, 2... Element area, 2'
...Near region of element region, 3...Conductive layer (lowest potential)
, 4...lowest potential power supply pad, 4'... pad,
5...Contact part, 5'...Contact hole, 6...1 conductive layer (lowest potential), 7, 8, 9
...Through hole, 10...Semiconductor substrate, 11...
...Element isolation oxide film, 12, 14, 16... Conductive layer (wiring), 17, 18, 19... Conductive layer (pad contact).
Claims (1)
素子分離を行なう酸化膜直下に基板と接する導電
層を設け、該導電層を所定の電位の電源パツドま
で延設したことを特徴とする半導体装置。 In a semiconductor device having an oxide film isolation structure,
1. A semiconductor device characterized in that a conductive layer in contact with a substrate is provided directly under an oxide film for element isolation, and the conductive layer is extended to a power supply pad at a predetermined potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16002088U JPH0281060U (en) | 1988-12-09 | 1988-12-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16002088U JPH0281060U (en) | 1988-12-09 | 1988-12-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0281060U true JPH0281060U (en) | 1990-06-22 |
Family
ID=31441726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16002088U Pending JPH0281060U (en) | 1988-12-09 | 1988-12-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0281060U (en) |
-
1988
- 1988-12-09 JP JP16002088U patent/JPH0281060U/ja active Pending