JPH0281063U - - Google Patents
Info
- Publication number
- JPH0281063U JPH0281063U JP1988160212U JP16021288U JPH0281063U JP H0281063 U JPH0281063 U JP H0281063U JP 1988160212 U JP1988160212 U JP 1988160212U JP 16021288 U JP16021288 U JP 16021288U JP H0281063 U JPH0281063 U JP H0281063U
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- mos transistor
- type mos
- basic unit
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
第１図及び第２図は本考案の夫々一実施例及び
一従来例の平面図、第３図は本考案を適用し得る
メモリセルの回路図である。
なお図面に用いた符号において、１１……メモ
リセル、１２……フリツプフロツプ、１３……ｎ
ＭＯＳトランジスタ、１６……インバータ、１８
……ｎＭＯＳトランジスタ、２２……ｐＭＯＳト
ランジスタ、３５……基本ユニツト素子である。
1 and 2 are plan views of an embodiment of the present invention and a conventional example, respectively, and FIG. 3 is a circuit diagram of a memory cell to which the present invention can be applied. In addition, in the symbols used in the drawings, 11...memory cell, 12...flip-flop, 13...n
MOS transistor, 16...Inverter, 18
. . . nMOS transistor, 22 . . . pMOS transistor, 35 . . . basic unit element.
Claims (1)
ランジスタとでメモリセルが構成されており、第
１の第１導電型ＭＯＳトランジスタと第２導電型
ＭＯＳトランジスタとから成るインバータを用い
て前記フリツプフロツプが構成されており、第２
の第１導電型ＭＯＳトランジスタが前記スイツチ
ング用トランジスタとなつているマスタスライス
方式の半導体メモリにおいて、 ゲート幅が互いに略等しい第１導電型ＭＯＳト
ランジスタと第２導電型ＭＯＳトランジスタとで
基本ユニツト素子が構成されており、 この基本ユニツト素子における前記第１導電型
ＭＯＳトランジスタが前記ゲート幅の方向に分割
されて前記第１及び第２の第１導電型ＭＯＳトラ
ンジスタとなつており、 前記基本ユニツト素子における前記第２導電型
ＭＯＳトランジスタが前記インバータにおける前
記第２導電型ＭＯＳトランジスタとなつているマ
スタスライス方式の半導体メモリ。 ２ 前記第１及び第２の第１導電型ＭＯＳトラン
ジスタの前記ゲート幅が約２対１となる様に前記
分割が行われている請求項１記載のマスタスライ
ス方式の半導体メモリ。[Claims for Utility Model Registration] 1. A memory cell is constituted by a flip-flop and a pair of switching transistors, and an inverter consisting of a first conductivity type MOS transistor and a second conductivity type MOS transistor is used to A flip-flop is configured and the second
In a master slice type semiconductor memory in which a first conductivity type MOS transistor is the switching transistor, a basic unit element is constituted by a first conductivity type MOS transistor and a second conductivity type MOS transistor having substantially equal gate widths. The MOS transistor of the first conductivity type in this basic unit element is divided in the direction of the gate width to form the first and second MOS transistors of the first conductivity type, and the MOS transistor of the first conductivity type in the basic unit element A master slice type semiconductor memory, wherein a second conductivity type MOS transistor serves as the second conductivity type MOS transistor in the inverter. 2. The master slice type semiconductor memory according to claim 1, wherein the division is performed such that the gate widths of the first and second first conductivity type MOS transistors are approximately 2:1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988160212U JPH0281063U (en) | 1988-12-09 | 1988-12-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988160212U JPH0281063U (en) | 1988-12-09 | 1988-12-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0281063U true JPH0281063U (en) | 1990-06-22 |
Family
ID=31442081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988160212U Pending JPH0281063U (en) | 1988-12-09 | 1988-12-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0281063U (en) |
-
1988
- 1988-12-09 JP JP1988160212U patent/JPH0281063U/ja active Pending
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