JPH0281132A - Program decoding circuit - Google Patents

Abstract

PURPOSE:To omit an external timing absorbing circuit and to decode a program without increasing the program capacity by using a register to which the cycle frequency is directly loaded and fixing the cycle frequency of each process of a branch instruction at a constant level. CONSTITUTION:The delay cycle frequency is previously coded to the instruction data having a small number of bits of a jumping destination in a program memory 11. While the prescribed cycle frequency is previously loaded to a register 18 when the increase of codes is impossible in the instruction data. A selection/memory means 19 stores the cycle frequency when coded cycle frequency exists in a decoding instruction data and the then stores the cycle frequency of the register 18 when the coded cycle frequency does not exist. A selection means 20 outputs the maximum cycle frequency in a CYC 16 among those cycle frequencies of each instruction and then outputs the set cycle frequency out of the means 19 when the conductions are satisfied at a decoder 17. As a result, the processing cycle frequency of the decoder 17 can be fixed at the same value for each process of a branching instruction.

Description

[Detailed Description of the Invention] ・ [Summary] Instruction execution procedures are executed within a digital signal processing LSI.
Regarding the 1Jill program decoding circuit, we aim to eliminate the need for an external timing absorption circuit and perform decoding without increasing the program volume. The output of the first instruction register is input to the second instruction register and the decoding section, the type of the instruction code decoded by the decoding section is determined, and the cycle number determining section determines the type of the instruction code. In a program decoding circuit in a digital signal processing LSI that outputs the corresponding cycle number and inputs it into the cycle number register, and executes the output instruction of the second instruction register with the number of cycles output from the cycle number register by a decoder, the number of cycles is determined. selects and stores one of the coded cycle number in the output of the first instruction register and the number of cycles from the register, based on the output of the decoding unit; a selection/storage means for selectively outputting the output of one of the selection/storage means and the cycle number register to the decoder as a processing cycle number, and a selection means whose switching is controlled by the output of the decoder. Configure it as follows.

(Industrial Application Field) The present invention relates to a program decoding circuit, and more particularly to a program decoding circuit that executes an instruction execution procedure in a digital signal processing LSI.

A digital signal processor 1 with a configuration as shown in FIG. 4 is used when encoding and compressing audio. ! LS I (hereinafter referred to as D
SP) 1 is used. This 08P1 is a program decoding circuit 2. which decodes the program and controls the instruction execution procedure. Generate address information and control each circuit section 11
111 part 3. Random access memory (RAM) for data storage4. Performance section 5. and input/output (
Ilo) section 6, which is connected to an internal bus 7.
It is connected to the.

When a branch instruction is implemented by a program in a DSP having such a configuration, as shown in FIG. 5, a manual branch instruction is determined (step SI), and if the determination conditions are not met, the first process is performed (step S2). . On the other hand, if the above judgment conditions are met, a second process is performed (step 83).
).

Here, since the first and second processes are different, the number of processing cycles is also different, and therefore the completion time varies due to the difference in the number of processing cycles.

For this reason, the timing of data input/output will vary, so it may be possible to eliminate the timing variation by adding a timing absorption circuit outside the DSP1. However, since the addition of this timing absorption circuit increases the circuit scale of the entire system, it is necessary to combine the number of processing cycles by the program decoding circuit 2 without using the timing absorption circuit.

[Conventional technology]

FIG. 6 does not show a block diagram of -1 of the conventional program decoding circuit. In the figure, 10 is a program counter (hereinafter referred to as P
It is incremented by 1 by an internal clock, and necessary address data is loaded when a branch instruction is executed.

11 is a program memory in which instructions are stored;
Contents of address specified by data from CIO
instruction data) into the first instruction register (hereinafter referred to as IR) 12. The output instruction data of the lR12 is fetched into the second lR13, and is decoded by the Im@ unit 14 to determine the type of instruction code.

Here, as shown in FIG. 7, the output of PClo is address n,
It is assumed that the address data is in the order of address n, address 11000+2, etc., and instruction data of a 3-cycle instruction, which is a branch instruction, is stored at address n. In this case, assuming that the cycle number extractor 15 does not exist, lR1
By extracting the 3-cycle instruction at address n from 2, the output of CYC16 changes as shown in FIG. 7 based on the output of decoder 14, and the output of lR13 changes as shown in the same figure.

Therefore, if the cycle number calculation unit 15 is not provided, the processing time will differ depending on the number of cycles determined by the hardware of the instruction.

On the other hand, when the cycle number calculation section 15 is set up,
The cycle number calculation unit 15 outputs the number of cycles determined by the program so that the number of cycles is the same in the two processes, and inputs it to the cycle number register (CYC16). A decoder (DEC) 17 executes the instruction data from the IR 13 in the number of cycles from the CYC 16, and outputs the data obtained thereby to the control unit 3 and the internal bus 7.

[Problem to be solved by the invention]

In the conventional program decoding circuit described above, in order to match the number of processing cycles between the two processes in the program shown in the flowchart shown in FIG. 5, a delay program must be further inserted into the program. Must be. For this reason, in the conventional program return 9 circuit, a delay program is required for each branch instruction, resulting in a problem that the program 8 mother becomes large.

The present invention has been made in view of the above points, and eliminates the need for an external timing absorption circuit, and furthermore, the present invention has a program capacity of ff1.
-t> An object of the present invention is to provide a program decoding circuit that can decrypt a program without having to transfer it.

(Means for Solving the Problems) A block diagram of the principle of the present invention is shown in FIG. In the same figure, the 6th
Components that are the same as those in the figures are given the same reference numerals, and their explanations will be omitted. The present invention provides a conventional program decoding circuit with a register 18 into which the cycle number is directly loaded, a selection/storage means 19, and a selector g220.

The selection/storage means 19 selects and stores one of the coded cycle number output from the first instruction register 12 and the cycle number from the register 18 based on the IA group unit 14 output.

Further, the selection means 20 mentioned above also has a cycle number register (CY
C) 18 and the output of the selection/storage means 19 are selectively outputted to the decoder (DEC) 17 as the number of processing cycles, and switching is controlled based on the output of the DECl 7.

(Function) Among the instruction data stored in the program memory 11, the number of delay cycles is coded in advance for instruction data that requires a small number of bits to jump to. When it is not possible to increase the number of codes in the program (for example, when the program size is too large), a predetermined number of cycles is loaded into the register 18 in advance.

As a result, the selection/storage means 19 stores the number of cycles coded in the instruction data decoded by the decoder 14, and stores the number of cycles in the register when there is no number of coded cycles. Store the number of cycles from 18 onwards.

The selection means 20 normally outputs the longest cycle number stored in the CYC 16 among the hardware-determined cycle numbers of each instruction that the original instruction has, but if the conditions are met in the decoder 17, The set number of cycles selectively stored in the selection/storage means 19 is selectively output.

Thereby, the number of processing cycles in the decoder (DEC) 17 can be fixed to the same value for each branch instruction processing. Also, this can be done with hardware rather than a delay program.

(Example〕 FIG. 2 shows a block diagram of one embodiment of the invention.

In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. In FIG. 2, among the instruction data stored in the program memory 11, instruction data that requires a small number of jump destination bits and whose number of cycles is shorter than other instructions is given the same cycle. The number of cycles is coded and added to make it a number.

On the other hand, the register (CYCRG) 1B is loaded with a preset number of cycles as described above. In addition, 22 is a selector, which is a cycle number register (CYC).
Together with 23, it constitutes selection/storage means 19.

When there is the number of cycles added to the instruction data from lR12, the selector 22 selects and outputs the added cycle number, and when there is no added cycle number, selects and outputs the cycle number from the register 18. do. The output cycle number of the selector 22 is input and held in the CYC 23.

The selector 24 prioritizes and outputs the original number of cycles determined by hardware that the instruction from CYCI 6 has, but depending on the conditions based on the output of the decoder 17,
The number of cycles held in the YC 23 is selectively outputted to delay the number of execution cycles of the decoder (DEC) 17.

FIG. 3 shows a time chart for explaining the operation at the time of a branch instruction in this embodiment. Assume that the output address data of PClo changes as shown in Fig. 3, and that a branch instruction and a 3-cycle instruction (branch destination address is address) is stored at address n of the program memory 11. do. PC
Based on the output address data of the IO, the instruction data read from the designated address of the program memory 11 is stored in the lR12 as shown in FIG. be done.

The cycle number calculation unit 15 calculates the number of cycles for the instruction data decoded by the decoding unit 14, and in the case of a decoded branch instruction at address n, 3” is input to CYCI6.This CYC
The input cycle number “3” of I6 is input to D through the selector 24.
Input to ECI 7.

At this time, the DECl 7 performs the condition judgment (step S+) shown in FIG. 5, and if the condition is satisfied (i.e.,
When performing the second process with a shorter number of cycles), the selector 24 is controlled to select and output a value obtained by subtracting 1 from the number of cycles (here m) stored in the CYC 23.

Like CYCI6, CYC23 has a subtraction function, and as shown in FIG. D.E.
Cl 7 executes an instruction using the cycle number from this selector 24, but during the cycle number output W1 of CYC 23, it is a know operation and does not process anything. Therefore,
The output of fR13 is as shown in FIG.

Thereby, by delaying and matching the shorter number of cycles to the longer number of cycles among the number of cycles for each process of a branch instruction, the number of cycles can be fixed at a constant value regardless of the branch instruction.

(Effects of the Invention) As described above, according to the present invention, the number of cycles for each process of a branch instruction can be fixed to a constant value without using a delay program, so that the increase in program time is almost negligible. Moreover, it has the advantage that the input/output timing of data for each process can be made constant without providing an external timing absorption circuit, and the structure of the DSP can be made smaller.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 3 is a block diagram of the principle of the present invention.
A time chart for explaining the operation of 1i2I, FIG. 4 is a configuration diagram of an example of a digital signal processing LSI, FIG. 5 is a 70-day diagram of processing using a branch instruction, FIG. 5 is a time chart of branch instructions when there is no cycle number calculation unit. In the figure, 1 is a digital signal processing LSI (DSP), 2 is a program decoding circuit, 10 is a program counter (PC), 11 is a program memory, 12 is a first instruction register, 13 is a second instruction register, and 14 is a second instruction register. Decoding unit, 15 is a cycle number calculation unit, 16.23 is a cycle number counter (CYC), 17 is a decoder (DEC), 18 is a register, 19 is a selection/recording I/R means, 20 is a selection means, 22゜24 indicates a selector.

Claims (1)

[Claims] The program counter (10) controls the program memory (
11) is input to the first instruction register (12), and the output of the first instruction register (12) is input to the second instruction register (13) and the decoding unit (14).
), the decoder (14) determines the type of the decoded instruction code, the cycle number calculator (15) outputs the corresponding cycle number, and the cycle number register (16)
The output command of the second instruction register (13) is input to the cycle number register (16) by the decoder (17).
Digital signal processing LSI that executes with the number of output cycles
In the program decoding circuit in the register (18) into which the cycle number is directly loaded, one of the coded cycle number in the output of the first instruction register (12) and the cycle number from the register (18) is loaded. , a selection/storage means (19) that selects and stores the selection based on the output of the decoding section (14); and an output of one of the selection/storage means (19) and the cycle number register (16) as the number of processing cycles. is selectively output to the decoder (17), and the decoder (17)
) A program decoding circuit characterized in that it comprises a selection means (20) whose switching is controlled by the output of the circuit.