JPH0281214A - Clock signal control circuit for microprocessor - Google Patents

Abstract

PURPOSE:To prevent a useless current consumption even if a processing speed of a microprocessor is increased by switching a period of a clock signal, when an operating speed of a memory and an I/O device is low and a waiting time is generated at the time of write and read-out of data. CONSTITUTION:Whether an execution cycle of a microprocessor is an execution cycle for an operation of the inside of the microprocessor, or that for other operation than an internal operation for executing write and read-out of a memory, an I/O device, etc. is discriminated by an execution cycle discriminating means 1. As a result, when the execution cycle is other execution cycle than the execution cycle of the internal operation, a clock signal selecting means 3 selects a clock signal of a slower period than usual in accordance with an access time of a device which becomes an object and supplies said signal to the microprocessor. Accordingly, at the time of the execution cycle for which it is unnecessary to operate it by a clock signal of a quick period, the microprocessor and each part of the circuit can be operated by a slow clock. In such a way, a useless power consumption can be prevented.

Description

[Detailed Description of the Invention] [1 Required] This invention relates to a clock signal control circuit that controls a clock supplied to a microprocessor, and which switches the frequency of the clock supplied to a microprocessor, enables the microprocessor to operate at high speed, and eliminates waste. The purpose of the present invention is to provide a clock signal control circuit for a microprocessor that eliminates current consumption. a clock signal generating means for dividing a 1-loss clock signal to generate signals of a plurality of frequencies; and when the execution cycle determining means determines that the execution cycle is an internal operation execution cycle, the clock signal generating means clock signal selection means for supplying a signal of a predetermined frequency to the microprocessor sensor as a system clock signal, and supplying a signal of a frequency lower than the predetermined frequency to the microprocessor when an execution cycle is other than an internal calculation execution cycle; The system is configured to have the following.

[Industrial application field]

The present invention relates to a clock signal control circuit that controls a clock supplied to a microprocessor.

[Conventional technology]

In a microprocessor that operates using a clock signal supplied from an oscillation circuit as a system clock, the processing speed of various operations is determined by the frequency of the system clock. Therefore, in order to achieve faster processing, it is sufficient to operate with a clock signal of a higher frequency.

However, when the clock frequency is set to high, Ilo and memory may not be able to respond. For this reason, conventionally, a wait cycle is provided to delay the operation of a microprocessor by a specific cycle for an element having a slow access time.

FIG. 4 is a diagram showing an example of the operation timing of the microprocessor, and the same figure shows the timing of a memory read cycle in which the microprocessor reads data from the memory.

A microprocessor is normally given a clock signal (shown in FIG. 2) with a constant period obtained by frequency-dividing the original oscillation clock signal shown in FIG. First, in the T+ state, address data of addresses "0 to 15" and "16 to 19" are output ((3) and (4) in the figure), and a memory address is specified. Further, during this TI state period, the address latch enable signal (ALE) becomes high level. Address data is then latched based on this ALE signal. Once the address is determined, the corresponding RAM address is accessed and data is read.

At this time, if the access time of the RAM being used is slow and the data is not output by the read timing of the microprocessor, a wait cycle T- is inserted to delay the data read timing.

The figure shows an example in which two wait cycles are inserted, and data can be read from the RAM by delaying reading for two clocks.

Conventionally, when accessing a RAM, an I10 device, etc. whose access time is slower than that of a microprocessor, it has been necessary to insert a wait cycle so that the microprocessor waits for output from another device.

[Problem to be solved by the invention]

As mentioned above, in conventional microprocessor systems, when writing or reading data to memory or I10 devices with slow access times, a wait cycle is inserted in the middle of the execution cycle, and memory or I10 devices have slow access times.
The reading or writing of data by the microprocessor is delayed until it becomes possible to write or read data from the 0 device. However, if a microprocessor or other IC driven by a clock signal is
When configured with SI, the current consumption increases when the signal level changes, so as the clock signal frequency increases, the current consumption of the circuit increases.
Therefore, the current consumption for each clock does not change even during the wait cycle, and there is a problem that current is wasted by the microprocessor or the like during the wait cycle.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock signal control circuit for a microprocessor that can operate the microprocessor at high speed by switching the frequency of the clock supplied to the microprocessor, and eliminates wasteful current consumption.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. In the figure, execution cycle determining means 1 determines the content of the execution cycle of the microprocessor, clock signal generating means 2 divides the generated reference clock signal to generate a plurality of frequency signals, and clock signal selecting means 3 When the execution cycle determining means 2 determines that the execution cycle is an internal operation execution cycle, the clock signal generation means 2 supplies a signal of a predetermined frequency to the microprocessor, and the execution cycle is determined to be other than the internal operation execution cycle. When it is determined that this is the case, a signal having a frequency lower than the predetermined frequency is supplied to the microprocessor.

[For production]

In the present invention, the execution cycle determination means 1 determines the contents of the execution cycle of the microprocessor, and determines whether the execution cycle is an operation inside the microprocessor or a memory,
It is determined whether this is an execution cycle other than internal calculations such as writing and reading Ilo. As a result of the determination, if the execution cycle is other than the internal calculation execution cycle, the clock signal selection means 3 selects a clock signal with a slower cycle than usual in accordance with the access time of the target device, and supply to.

Therefore, during an execution cycle when it is not necessary to operate with a fast-cycle clock signal, the microprocessor and each part of the circuit can be operated with a slow clock, thereby eliminating unnecessary power consumption.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 2 to 4.

FIG. 2 is a block diagram of a clock control circuit according to an embodiment of the present invention. A 0 oscillator 11 is a circuit that generates an original oscillation clock signal as a reference. The frequency dividing circuit 12 is the oscillation circuit 11
This is a circuit that divides the frequency of the clock signal from the clock signal, and outputs the clock signal with a different period obtained by frequency division to the clock selection circuit 13.

The clock selection circuit 13 is a timing generation circuit 1 which will be described later.
According to the signal from 6, a clock signal of a specific period is selected and output to the CPU 14.

Based on the clock signal from the clock selection circuit 13, the CPU 14 writes and reads data to and from a RAM (not shown) and the (10) device. Data indicating whether it is writing or reading from memory, etc. as status information---Tz
Output as .

The execution cycle determination unit 15 decodes the status information So to S2 from the CPU 14 and determines whether the execution cycle is
internal calculation execution cycle or memory read cycle,
It is determined whether it is a write cycle, etc., and the determination result is output to the timing generation circuit 16. The timing generation circuit 16 determines the memory and I10 to be written or read based on the determination result of the execution cycle determination unit 15.
This circuit instructs the clock selection circuit 13 which period of the clock signal to select and output according to the access time of the device.

Next, the operation of the above circuit will be explained with reference to the memory read cycle timing chart of FIG.

The oscillator 11 in FIG. 2 generates an original oscillation clock signal with a period shown in FIG. A clock signal (shown in FIG. 3(1)) is supplied.

Now, in the T+ state, as shown in FIG. 3 (2), the CPU 14 sends the status information -3-0=1,
When the data s, -o, and X2-1 are output, the execution cycle determining unit 15 determines that the current execution cycle is a memory read cycle, and notifies the timing generation circuit 16 of the determination. During a memory read cycle, the timing generation circuit 16 selects the target R as instructed by the CPU 14.
The clock selection circuit 13 is instructed to switch to a clock signal with a period corresponding to the AM access time. As a result, the clock selection circuit 13 supplies the CPU 14 with a clock signal having a period T2' longer than the normal operation period T1 from the next T2 state, as shown in FIG. 3(3), and this long period clock signal is It is supplied until the next T3 state. During this time, data is output from the RAM with slow access time at the timing shown in (4) in the figure, and the CPU 1
It becomes possible to read data from 4.

In the next T4 state, the original short period T4 (='r
+) clock signal, and the data in the RAM is taken into the CPU 14 at the rising edge of the read signal H shown in FIG. 5 (5).

That is, status information output from the CPU 14. ～Determine the content of the execution cycle from T2, and
When the cycle is not an internal calculation execution cycle, the cycle of the clock signal supplied to the CPU 14 is switched depending on the access time of the target memory or (10) device.

For example, when the execution cycle is a read or write cycle to memory, if the access time of the memory being used is fast and data can be read or written within one machine cycle, then T Provides a clock signal. On the other hand, when the access time of the memory being used is slow and data cannot be read or written within one normal machine cycle, a clock signal with a slow cycle corresponding to the access time of the memory is supplied.

As described above, even when a memory with a slow access time is used, each part of the circuit including the CPU 14 can be operated with a clock signal having a cycle matching the access time. Therefore, even while the CPU 14 is waiting for data output from the memory as in the conventional case, it is possible to operate the CPU 14 with a clock signal having a fast cycle, thereby preventing unnecessary consumption of current.

Although the above embodiment describes the case of memory access, the clock signal is similarly switched to reduce circuit consumption in the case of the I10 read/write cycle for an I10 device that requires a long time to read/write data. Current can be reduced. For example, when it is determined that it is an I10 read or write cycle in the T1 state, the clock signal is switched to a slower cycle clock signal from the T2 state onward, and the slow cycle clock signal is used for subsequent machine cycles until an instruction is received from the CPU 14. will continue to be supplied.

and! 10 When access to the device is completed, the CP
From U14 to timing creation circuit 16! 10 The end of the read/write cycle is notified, and the clock signal is switched.

〔Effect of the invention〕

According to the present invention, when the operating speed of the connected memory or I10 device is slower than the operating speed of the microprocessor and there is a waiting time for writing or reading data, the clock signal is Since the cycle is switched, the processing speed of the microprocessor itself can be increased and wasteful current consumption by the microprocessor can be eliminated.

FIG. 3 is a timing chart showing the operation of the embodiment; FIG. 4 is a timing chart showing the conventional operation.

l... Execution cycle determination means, 2... Clock signal generation means, 3...Clock signal selection means.

Claims (1)

[Scope of Claims] Execution cycle determining means (1) for determining the content of an execution cycle of a microprocessor; and clock signal generating means (2) for dividing a generated reference clock signal to create signals of a plurality of frequencies. ), and when the execution cycle determining means (1) determines that the execution cycle is an internal calculation execution cycle, a signal of a predetermined frequency from the clock signal generating means (2) is sent to the microprocessor as a system clock signal. clock signal selection means (3) for supplying a signal with a frequency lower than the predetermined frequency to the microprocessor when the execution cycle is determined to be other than an internal operation execution cycle. clock signal control circuit.