JPH0281639A - Print pattern generation method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a serial dot printer equipped with a rotatable print head, which can be set at any angle with respect to the direction of movement and can be generated at high speed. This paper relates to a printing pattern generation method.

[Conventional technology]

Recently, many proposals have been made for printing by tilting printing elements arranged in a row and for printing reduced/enlarged characters. However, in this case, the problem when actually printing is that the printing element (dot pin) of the print head
Since it takes time to generate a dot pattern corresponding to the array, this has become a bottleneck in processing speed.

Conventionally, in dot matrix printers.

As a method for printing arbitrary character sizes, there is, for example, a method described in Japanese Patent Application Laid-Open No. 176852/1983. This system tilts a print head equipped with a plurality of dot bins for dot-to-matrix printing at an arbitrary angle with respect to the direction of head movement, and is equipped with means for controlling print point timing that occurs according to the inclination angle of the print head. This is a correction. That is, first, the rotation angle corresponding to the printing reduction ratio is calculated, and the print head is rotated by this rotation angle, while the print timing correction value of the printing point corresponding to the reduction ratio is output, and the horizontal direction of the printing section is By moving the dots and rotating the rotation angle of the print head, the printing point interval in the vertical direction is reduced and the printing timing of the same dot row is synchronized.

[Problems to be Solved by the Invention] However, in the above-mentioned prior art, there is no description of the details of print point timing control.

By the way, the method of forming characters in a dot matrix printer is performed by selectively operating each printing element at each point on a grid, as shown in FIG. This timing control of the printing points controls each printing element arranged diagonally.

It is necessary to control the elements as if they were arranged vertically on this grid. For this purpose, a practical method is to correct the lateral deviation of each printing element in units of drive control cycles of each printing element.

FIG. 5 is a diagram showing an example of printing when the print head is rotated.

As shown in Figure 5, in this method, the interval between each printing element in the horizontal direction (here, the interval between the inclined solid circles) is determined by the grid dimension (here, the interval between the solid line double circle and the adjacent broken line circle). (distance)), and print data is given to each print element shifted by this dimension.

Each printing element is driven at the same timing. Note that in FIG. 5, the spacing between printing elements in the horizontal direction is not an integral multiple of the grid size, but is approximately 1.5 times the grid size.

In reality, it is multiplied by 6 to 8 times. The method of applying this print data to each print outline by shifting it in drive control cycle units is to use a microprocessor to convert the print data into drive data according to the amount of deviation of each print element, and then apply it to the print element drive unit. There is a way.

This method is usually employed in serial dot printers in which printing elements are arranged in two staggered rows, as described in, for example, Japanese Patent Laid-Open No. 183163/1983.

FIG. 6 is a flowchart showing a conventional control method for a serial dot printer, and FIG. 2 is a diagram showing an example of print data before conversion and drive data after conversion by the control method of FIG.

FIG. 6 shows a procedure for converting print data into drive data when the print head is tilted at a certain predetermined angle using the method described above.

The results of the conversion process in FIG. 6 are shown in FIG. 2.

In FIG. 6, first, the start address of the print data is
Store it in the NGI (print) register (step 101),
The drive data storage start address is stored in the 5ET (set) register (step 102).

Next, set the C register (count register) to Ol (step 103), move the contents of the INGI register to the A register (accumulator) (step 104),
The start address of the deviation correction data (1) is stored in the HO3E (correction) register (step 105). Move the contents of the HO5E register to the B register (the other accumulator) (step 106), store the sum of the contents of the SET register and the B register in the WSET (write set) register (step 107), and then: A
AND the contents of the register and the C register,
Store the result in the D register (step 108), W
Move the contents of the SET register to the E register (step 1)
09). Also, the contents of the D register and the contents of the E register are ORed and stored in the WSET register (step 1
10). Next, the contents of the C register are shifted to the upper bit by one bit (step 111). That is, the C register is a register for extracting dot data one bit at a time. Here, only the lower pit is shifted by 1 bit.The HO8E register is incremented by 1 (step 112), and the C register carrier flag is set to 1'.
If it is 0', the process branches to step 106, and if it is 1', the process proceeds to the next step. Next, I
Check that the NGI register is not the final address (
Step 114), after incrementing the ING register and the SET register (steps 115 and 116),
The process branches to step 103. Note that if the INGI register is the final address, the process ends.

As is clear from the conversion process flow in Figure 6, converting one dot requires three memory accesses, five operations, and one judgment, which slows down the processing speed and makes it extremely practical. It wasn't.

Also, as a method of shifting the print data in drive control cycle units and applying it to each print element, it is possible to use a shift register, but in order to increase the reduction/enlargement value,
Increase the spacing between printing elements.

In addition, it is necessary to increase the amount of tilting, and in that case, the number of stages of the shift register increases. Furthermore, since it is necessary to vary the number of stages in the shift register depending on the inclination of the print head, there are problems such as an increase in the amount of circuitry.

The purpose of the present invention is to solve these conventional problems and to drive print data according to the amount of deviation of each printing element without increasing the amount of circuitry in a serial dot matrix printer equipped with a rotatable print head. The object of the present invention is to provide a printing pattern generation method that can be converted into data at high speed.

[Means to solve the problem]

In order to achieve the above object, the print pattern generation method of the present invention uses a serial dot matrix in which the print head is rotatable in order to set the arrangement direction of print elements at an arbitrary angle with respect to the moving direction of the print head. The printer includes a memory element that stores a value converted from print data to drive data corresponding to the amount of deviation of the printing element, a first latch circuit that latches the print data, and a a selector for selecting data and data read from the memory element; a second latch circuit for latching a storage start address for storing drive data converted from print data in the memory element;
an address correction storage means storing an address correction value of the memory element corresponding to the angle of the print head and the bit position of the print data, and an address corresponding to the angle of the print head as an address of the address correction storage means; a third latch circuit that specifies an address in which a correction value is stored; and an adder that adds the contents of the second latch circuit and the output data from the address correction storage means and outputs the result as an address of the memory element. and a control signal generating means for generating a timing control signal for controlling each of the above-mentioned constituent means.

[For production]

In the present invention, a print head equipped with a plurality of print elements having a predetermined arrangement is moved in a predetermined direction and these print elements are selectively operated to form a combination of dots on a print medium. In a serial dot matrix printer that prints information, the print head is rotatable in order to set the arrangement direction of these printing elements at an arbitrary angle with respect to the direction of movement of the print head, and the information is stored in a memory element. The print data of the print element group shown in FIG. 2(a) thus obtained is converted into drive data shown in FIG. 2(b), and then stored in the memory element again.

In Figure 2(b), the print head is set at a predetermined angle and an integer fraction (1/6 to 1
/8). Therefore, for example, when the print head is set at a predetermined angle, if the amount of lateral deviation between each print element is an amount equivalent to 2 of the drive control period unit of the print element, the address correction storage To.

As shown in Figure 3, sequentially from address (8o)□6.

(O),. ,(2),. ,(4),. , . . , are stored in advance, read out sequentially, and the memory element is accessed using the value added to the first storage address, thereby reading out 1 to 8 bits of correction data for each column. The read correction data is replaced with print data bit by bit by the selector, and then stored in the memory element again. As a result, character pattern drive data for columns 1 to 8 shown in FIG. 2(b) are stored in the memory element.

Therefore, by sequentially reading these and driving the printing elements, the pattern shown in FIG. 2(b) can be obtained.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a print pattern generation device showing an embodiment of the present invention.

In FIG. 1, 1 is a memory element that converts print data into drive data according to the amount of deviation of the print element and stores it, 2 is a latch circuit that latches the print data, and 3 is a circuit that converts print data into drive data. To.

The three bit position designation lines 7 output from the timing generator 6 are decoded, and the print data latch 2 is
4 is a memory element write data latch circuit that latches the data output from selector 3, 5 is a data bus driver that drives the data bus, and 8 is an address terminal of memory element 1. This is an address multiplexer for output. Address multiplexer 8 converts print data into drive data, and when reading drive data to the outside, adder 9
The address bus 13 driven by a microprocessor (not shown) is controlled to provide the output of the address bus 13 to the memory element 1. Further, 9 is an adder that adds the contents of the storage head address latch 11 and the output data of the address correction ROM 10, and 10 is an address correction value of the memory element 1 corresponding to the angle of the print head and the bit position of the print data. This is an address correction ROM that stores . Address supplement iROM 10
A bit position designation line 7 outputted from the timing generator 6 is inputted to the lower three bits of the address terminal of , and thereby the address of the memory element 1 corresponding to the bit position of the print data at a predetermined angle is corrected. Specifies the location where the value is stored.

In addition, the address terminals of the 4th pin and above of the address correction ROM10 have a memory element 1 for each angle of the print head.
The output of a correction ROM address latch 12 for specifying the location where the address correction value of is stored is input. 12 is a latch circuit that stores the address of the address correction ROM10. The timing generator 6 generates timing signals for controlling each of the above components when converting print data into drive data. For example, it generates a read signal, a write signal, etc. for the memory element 1.

The timing generator 6 is driven by a microprocessor (not shown) outputting print data to the print data latch circuit 2, converts the print data of the print data latch circuit 2 into drive data, and stores this in the memory. Element 1
When the storage is finished, the series of timing generation operations is stopped.

In this way, the print pattern generating device of the present invention includes a memory element 1 that converts print data into drive data corresponding to the amount of deviation of each print element and stores it, and a first latch circuit 2 that latches the print data. , a selector 3 for selecting data read from the memory element 1 and data from the first latch circuit 2, and a storage start address for converting print data into drive data and storing it in the memory element 1. a second latch circuit 11 for latching, and an address correction storage section (ROM) that stores address correction values of the memory element 1 corresponding to the angle of the print head and the bit position of the print data.
10, a third latch circuit 12 that acts as an address of the address correction storage section 10 and specifies an address in which an address correction value corresponding to the angle of the print head is stored, and the contents and address of the second latch circuit 11. It is comprised of an adder 9 that adds output data from the correction storage section 10 and outputs it as an address of the memory element 1, and a timing signal generation section 6 that controls each component.

The general operation of FIG. 1 will be described.

The first latch circuit 2 receives the print data, and the second latch circuit 11 receives the storage start address of the drive data.

In addition, the third latch circuit 12 stores the address where the address correction value determined by the angle of the print head is stored.
Next, the timing generator 6 is activated, and the contents of the second latch circuit 11 and the output of the address correction storage unit 10 (however, the output data at this time is 0) are added to the adder 9. and give this as the address of memory element 1. The memory element 1 executes a read operation according to the timing from the timing generator 6 and inputs this value to the selector 3. The selector 3 selects the first latch circuit 2 from the read data of the first latch circuit 2 and the memory element 1.
As for the remaining second bit data, read data from the memory element 1 is selected and output. The output of selector 3 is.

At the next timing of the timing generator 6, the memory element 1
is stored in When the storage in the memory element 1 is completed, the timing generation section 6 advances the address in the address correction storage section 10 by one, and the output of the address correction storage section 10 is added by the adder 9. At this time, the address correction storage section 10 outputs the amount of deviation between the first printing element and the second printing element.

Thereafter, in the same way, each time the address in the address correction storage unit 10 is incremented by 1, the amount of deviation between the first printing element and the third printing element, and the difference between the first printing element and the fourth printing element. The amount of deviation, ... is output, and these data are sent to the adder 9.
is added as the address of the memory element 1. The memory element 1 executes a read operation each time, and inputs read data to the selector 3. The selector 3 synchronizes with the address of the address correction storage section 10,
As mentioned above, the first bit of data is the first
The data of the latch circuit 2 of
The other bits select read data from memory element 1 and store it in memory element 1. Below, the first
The same operation is repeated for the number of bits latched by the latch circuit 2, and the print data is converted into drive data and stored in the memory element 1.

FIG. 7 is an operation flowchart of FIG. 1, and FIGS. 2 and 3 are diagrams for explaining the operation of FIG. 1.

Although the outline of the operation shown in FIG. 1 has been described above, it will be explained in more detail, including the preparation process.

First, the angle of the print head is determined according to the character size information or vertical character density information specified by the host device, and then data corresponding to this angle is selected and the correction R is performed.
Set in OM address latch 12. Here, the angle of the print head is A, and the address correction value of the memory element 1 corresponding to A is the address (80
)1i address, the correction RO
Data (80), s is set in the M address latch 12 (step 203).

On the other hand, the print data is as shown in FIG.

In other words, if the amount of lateral deviation between each printing element when the angle of the print head is A is an amount corresponding to 2 of the drive control period unit of the printing element, as shown in Fig. 3. , address correction ROM10 contains atto L/X (8
0) 1G Ka et al (0) (0),. , (2) 1°, (4)!
. ,(8),. , . . . 8 bytes of data are sequentially stored.

With this preparation completed, when the operation is started, first, the print data in column 2 in FIG. 2 is output to the print data latch circuit 2 and set (step 201). The start address of the drive data is also set in the storage start address latch circuit 11 (step 202), and since (8o)is is set in the correction ROM address latch circuit 12 first (step 203), the timing The generation unit 6 is activated (step 204), and the timing generation unit 6 transfers (0) to the bit position designation line 7. is output.

This is the start of operation at n=1 in FIG.
The timing for writing the drive data of the first bit of the 0th column in FIG. is output, and this value is added to the contents of the storage head address latch 11 by the adder 9 and inputted to the memory element 1 as an address (step 206). Next, the timing generator 6 provides a read signal to the memory element 1.

Read data from memory element 1 (step 207)
. When this read data of the memory element 1 is input to the selector 3, the bit position designation line 7 from the timing generator 6 is set to (0) in the selector 3.

By doing so, the first (2') bit in the data from print data latch 2 is selected as the first bit output data, and the other output bits are the corresponding read bit data from memory element 1. (Step 20)
8). The output from the selector 3 is latched by the memory element write data latch 4, and is generated by the write signal issued from the timing generator 6 following the read signal.
The data is written to memory element 1 (step 209). Next, the timing generator 6 sends (1) to the bit position designation line 7.
□. Output. That is, the operation moves to the write operation of the second bit of the drive data in column 0 in FIG. 2(a). The value of the address correction ROM address latch 12 is incremented by 1 (step 210) and becomes n+1. At this time, the difference from the previous time is that (2
),. is output, and the address value obtained by adding 2 to the address at which the previous read/write was executed is input to the memory element 1.

In FIG. 7, when the value n+1 does not exceed the number of bits set in the first latch 2, step 2
The process branches to step 06, and the processes from 206 to 211 are repeated (step 211).

When n=2, the selector 3 outputs the second (21) bit as the output data, and outputs the second (2”) bit of the print data latch 2.
) bit data, and other output bits are stored in memory element 1.
The corresponding read bit data are selected respectively.

Next, when n=3, the selector 3 outputs the third (2”) bit as the output data, and the third (2”) bit of the print data latch 2
The data of the 2''th bit is selected, and the corresponding read bit data from the memory element 1 is selected for the other output bits.

By performing the above operation a total of 8 times, as shown in Fig. 2 (a)
The data in column 2 is converted into drive data as shown in column 2' in FIG. 2(b) and stored on the memory element 1. Hereafter, after incrementing the contents of the storage start address latch 11 by 1, the print data in the (■ column) of FIG.
Furthermore, by latching the print data in column 2 in the print data latch 2, drive data as shown in FIG. 2(b) is converted and stored on the memory element 1.

In this way, in this embodiment, the conversion process for one dot requires only one reading and one writing access to the memory element, and only one addition operation. Therefore, the conversion processing speed is significantly improved compared to the conventional method. Furthermore, since no shift register is used, there is no need to increase the number of stages, and the amount of circuitry can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, in a serial dot matrix printer equipped with a rotatable print head, print data can be converted into drive data corresponding to the amount of deviation of each print element at a higher speed than before. is possible,
It also has the advantage of requiring less circuitry.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the operation of FIG. 1, and FIGS. 4 and 5 are diagrams when the print head is rotated. FIG. 6 is a control flowchart for conventional print data conversion, and FIG. 7 is a flowchart of conversion operation to drive data in the present invention. 1: Memory element, 2: Print data latch circuit (first latch), 3: Selector, 4: Write address latch,
5: Data pie driver, 6: Timing generator, 7:
Bit position designation line, 8 near address multiplexer, 9:
Adder, 10 Near address correction ROM, 11: Storage start address latch circuit (second latch), 12 Near address correction ROM address latch circuit (third latch), 13:
Address bus from microprocessor. Figure Figure B -4 -4-〇

Claims (1)

[Claims] 1. In order to set the arrangement direction of the printing elements at an arbitrary angle with respect to the moving direction of the print head, in a serial dot matrix printer in which the print head is rotatable, according to the amount of deviation of the printing elements from the print data, a memory element that stores a value converted to drive data, a first latch circuit that latches the print data, data from the first latch circuit, and data read from the memory element. a second latch circuit that latches the storage start address for storing the drive data converted from the print data in the memory element, and a second latch circuit that corresponds to the angle of the print head and the bit position of the print data. an address correction storage means in which an address correction value of the memory element is stored; and a third latch for specifying, as the address of the address correction storage means, an address in which an address correction value corresponding to the angle of the print head is stored. a circuit, an adder that adds the contents of the second latch circuit and the output data from the address correction storage means and outputs the result as an address of the memory element, and generates a timing control signal for controlling each of the constituent means. 1. A printing pattern generation method comprising: a control signal generating means for generating a control signal.