JPH0282052U - - Google Patents
Info
- Publication number
- JPH0282052U JPH0282052U JP16170488U JP16170488U JPH0282052U JP H0282052 U JPH0282052 U JP H0282052U JP 16170488 U JP16170488 U JP 16170488U JP 16170488 U JP16170488 U JP 16170488U JP H0282052 U JPH0282052 U JP H0282052U
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base
- base layer
- emitter
- thyristor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 239000003708 ampul Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Thyristors (AREA)
Description
第１図は本考案の一実施例の説明図、第２図は
実施例の製造に使用される石英封管法の説明図、
第３図は従来例の縦断面図、第４図から第６図ま
での各図はゲートターンオフの特性図、第７図は
不純物濃度分布の曲線図である。
１……Ｐエミツタ層、２……Ｎベース層、３…
…Ｐベース層、４……Ｎエミツタ層、１１……Ｐ
ベース補正層、２１……アンプル管、２２……Ｓ
ｉウエハ、２３……ＧａＧｅ拡散源。
Fig. 1 is an explanatory diagram of one embodiment of the present invention, Fig. 2 is an explanatory diagram of the quartz sealing tube method used in manufacturing the embodiment,
FIG. 3 is a vertical cross-sectional view of the conventional example, each of the figures from FIG. 4 to FIG. 6 is a characteristic diagram of gate turn-off, and FIG. 7 is a curve diagram of impurity concentration distribution. 1...P emitter layer, 2...N base layer, 3...
...P base layer, 4...N emitter layer, 11...P
Base correction layer, 21... Ampoule tube, 22...S
i wafer, 23...GaGe diffusion source.
Claims (1)
Ｎエミツタ層を積層したプレナー型の表面ゲート
構造をもつたゲートターンオフサイリスタにおい
て、前記Ｐベース層に、該Ｐベース層より表面濃
度が高く、かつ拡散深さが前記Ｎエミツタ層より
も浅いＰベース補正層を設けたことを特徴とした
ゲートターンオフサイリスタ。 In a gate turn-off thyristor having a planar surface gate structure in which a P emitter layer, an N base layer, a P base layer and an N emitter layer are laminated, the P base layer has a surface concentration higher than that of the P base layer and a diffusion layer. A gate turn-off thyristor comprising a P base correction layer having a shallower depth than the N emitter layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16170488U JPH0282052U (en) | 1988-12-13 | 1988-12-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16170488U JPH0282052U (en) | 1988-12-13 | 1988-12-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0282052U true JPH0282052U (en) | 1990-06-25 |
Family
ID=31444881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16170488U Pending JPH0282052U (en) | 1988-12-13 | 1988-12-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0282052U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57201078A (en) * | 1981-06-05 | 1982-12-09 | Hitachi Ltd | Semiconductor and its manufacture |
| JPS63131574A (en) * | 1986-11-21 | 1988-06-03 | Hitachi Ltd | semiconductor switching equipment |
| JPS63209167A (en) * | 1987-02-26 | 1988-08-30 | Hitachi Ltd | Manufacturing method of semiconductor device |
-
1988
- 1988-12-13 JP JP16170488U patent/JPH0282052U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57201078A (en) * | 1981-06-05 | 1982-12-09 | Hitachi Ltd | Semiconductor and its manufacture |
| JPS63131574A (en) * | 1986-11-21 | 1988-06-03 | Hitachi Ltd | semiconductor switching equipment |
| JPS63209167A (en) * | 1987-02-26 | 1988-08-30 | Hitachi Ltd | Manufacturing method of semiconductor device |