JPH0282173A - In-circuit testing method for package circuit board - Google Patents
In-circuit testing method for package circuit boardInfo
- Publication number
- JPH0282173A JPH0282173A JP63235655A JP23565588A JPH0282173A JP H0282173 A JPH0282173 A JP H0282173A JP 63235655 A JP63235655 A JP 63235655A JP 23565588 A JP23565588 A JP 23565588A JP H0282173 A JPH0282173 A JP H0282173A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- circuit
- test
- circuit board
- probe pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Supply And Installment Of Electrical Components (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の目的]
(産業上の利用分野)
本発明は、実装回路基板のインサーキッドテスト法に係
り、特に、フラットパッケージ型IC素子等、表面実装
型電子部品を表面に搭載、実装して成る実装回路基板の
インサーキッドテスト法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to an incircuit test method for mounted circuit boards, and in particular, for testing surface-mounted electronic components such as flat packaged IC devices. This paper relates to an in-circuit test method for a circuit board mounted on and mounted on a board.
(従来の技術)
電子回路の小型化乃至高密度化を目的として、例えば、
二方向リード端子付きフラットパッケージ型IC素子や
、四方向リード端子付きフラットパッケージ型IC素子
等の表面実装型電子部品を、印刷回路基板の主面上に、
搭載乃至実装して構成した高密度実装回路基板が開発、
使用されている。(Prior art) For the purpose of miniaturizing and increasing the density of electronic circuits, for example,
Surface-mount electronic components such as flat package IC devices with two-way lead terminals and flat package IC devices with four-way lead terminals are placed on the main surface of a printed circuit board.
Developed a high-density mounting circuit board that is mounted or assembled.
It is used.
しかして、この種の高密度実装回路基板を製品とし、実
用に供するに当たっては、当然のことながら、上記高密
度実装回路基板が所要の機能を、十分に備えているか否
かを、Pめ試験、FP価している。つまり、前記高密度
実装回路基板に、その実装回路のインサーキッドテスト
が可能なパッドを予め設けておき、このパッドとプロー
ブピンとを接触させて、上記インサーキッドテストを行
っている。However, when making this type of high-density mounted circuit board into a product and putting it into practical use, it is a matter of course that P-level tests are carried out to determine whether the high-density mounted circuit board is sufficiently equipped with the required functions. , FP value. That is, the high-density mounting circuit board is provided in advance with a pad capable of performing an in-circuit test of the mounted circuit, and the in-circuit test is performed by bringing the pad into contact with a probe pin.
(発明が解決しようとする課題)
ところで、上記高密度実装回路基板について、前記イン
サーキッドテスト用のパッドを予め設けておくことは、
電子部品を実装する印刷回路基板の層構成を増すことに
なる。即ち、印刷回路基板の構成がそれだけ複雑になり
、設計コスト及び基板コストが高くなり、量産的にも不
経済である。(Problems to be Solved by the Invention) By the way, providing the pads for the incircuit test in advance on the high-density mounting circuit board has the following problems:
This increases the layer structure of the printed circuit board on which electronic components are mounted. That is, the structure of the printed circuit board becomes more complicated, the design cost and the board cost increase, and it is uneconomical in terms of mass production.
従って、本発明は、前記高密度実装回路基板のコストア
ップを招かず、かつ簡易に所要のインサーキッドテスト
を行い得る方法を提供することを目的とする。Therefore, an object of the present invention is to provide a method that does not increase the cost of the high-density mounting circuit board and can easily perform the required in-circuit test.
[発明の構成]
(課題を解決するための手段)
本発明は、所要の表面実装型電子部品を表面に実装して
成る実装回路基板のインサーキッドテストにおいて、前
記実装された表面実装型電子部品のリード部に、プロー
ブピン先端面を20〜50grの圧力で対接させてイン
サーキッドテストを行うことを特徴とする。[Structure of the Invention] (Means for Solving the Problems) The present invention provides an in-circuit test for a mounted circuit board on which required surface-mounted electronic components are mounted. The in-circuit test is carried out by bringing the tip end surface of the probe pin into contact with the lead part under a pressure of 20 to 50 gr.
(作 用)
上記の様に本発明のインサーキッドテスト法によれば、
実装された表面実装型電子部品のリード部に、プローブ
ピン先端面を20〜50g「の圧力で対接させて、所要
の電気的な接続を行なう。しかして、前記プローブピン
先端面の対接は、所定の力で圧接した形でなされるため
、電気的な接続も確実に維持されるばかりでなく、前記
圧接する力も比較的小さいため、対接させた表面実装型
電子部品のリード部の浮きも、容易に発見出来る。つま
り、高密度実装回路基板について、回路的な試験、評価
だけでなく、実装された表面実装型電子部品のリード部
の半田付不良箇所等も検出しうる。(Function) As described above, according to the incircuit test method of the present invention,
The tip end surface of the probe pin is brought into contact with the lead portion of the mounted surface mount type electronic component under a pressure of 20 to 50 g to establish the required electrical connection. Since this is done by pressing with a predetermined force, the electrical connection is not only maintained reliably, but also because the pressing force is relatively small, the leads of the surface-mounted electronic components that are in contact with each other are In other words, it is possible to detect not only circuit tests and evaluations of high-density mounted circuit boards, but also defects in soldering in the leads of mounted surface-mounted electronic components.
(実施例)
以下、第1図及び第2図を参照し、本発明の詳細な説明
する。第1図は表面実装型電子部品例えば、二方向リー
ド端子付きフラットパッケージ型IC索子1を、印刷回
路基板2の所定面に実装して成る高密度実装回路基板の
一部を側面的に示したものである。しかして、この高密
度実装回路基板のインサーキッドテストに当たっては、
予め用意しであるインサーキット用プローブピン3の先
端面3aを、前記フラットパッケージ型IC素子1のリ
ード1aに圧力20〜50grの範囲内で対接させる。(Example) The present invention will be described in detail below with reference to FIGS. 1 and 2. FIG. 1 shows a part of a high-density mounting circuit board in which a surface-mounted electronic component, for example, a flat package IC cable 1 with two-way lead terminals, is mounted on a predetermined surface of a printed circuit board 2. It is something that However, in the incircuit test of this high-density mounted circuit board,
The tip surface 3a of the in-circuit probe pin 3 prepared in advance is brought into contact with the lead 1a of the flat package type IC element 1 under a pressure of 20 to 50 gr.
ここで、インサーキット用プローブピン3の先、烟面3
aと、フラットパッケージ型IC素子1のリード1aと
の対接は、成るべくフラットパッケージ型IC素子1側
とする。また、前記インサーキット用プローブピン3の
先端面3aは、前記フラットパッケージ型IC素子1の
リードlaの対接面と、十分に接触し易い様な形に適宜
設定しておくことが好ましい。第2図は、上記インサー
キット用プローブピン3の先端面3aと、フラットパッ
ケージ型IC素子1のリード1aとを対接させた状態を
拡大して示す斜視図である。なお、第1図において、4
は、フラットパッケージ型IC素子1のリード1aを半
田付け5したパッド部である。Here, the tip of the in-circuit probe pin 3, the smoke surface 3
A and the lead 1a of the flat package type IC element 1 should be in contact with each other on the flat package type IC element 1 side as much as possible. Further, it is preferable that the tip end surface 3a of the in-circuit probe pin 3 is appropriately set in a shape so that it can easily come into contact with the contact surface of the lead la of the flat package type IC element 1. FIG. 2 is an enlarged perspective view showing a state in which the tip end surface 3a of the in-circuit probe pin 3 and the lead 1a of the flat package type IC element 1 are brought into contact with each other. In addition, in Figure 1, 4
1 is a pad portion to which a lead 1a of a flat package type IC element 1 is soldered.
上記の様にインサーキット用プローブピン3の先端面3
aを、フラットパッケージ型IC素子1の複数の所定リ
ード1aに各々対接させて、実装されている個々のフラ
ットパッケージ型IC素子1あるいは、実装されている
他の電子部品との複合系のインサーキッドテストを行う
。このインサーキッドテストにおいて、実装されている
個々のフラットパッケージ型IC素子1あるいは、実装
されている他の電子部品との複合系の試験、評価はなさ
れるが、前記インサーキット用プローブピン3の先端面
3aを対接させたフラットパッケージ型IC索子1の所
定リードlaの半田付不良も検知出来る。即ち、上記リ
ード1aに対するインサーキット用プローブピンの対接
圧力は、20〜50grと比較的小さいため、前記リー
ドlaが半田付不良で不導通状態にある場合(リードの
lfき)も容易に検出される。As shown above, the tip surface 3 of the in-circuit probe pin 3
a to each of the plurality of predetermined leads 1a of the flat package type IC element 1, so that each of the mounted flat package type IC elements 1 or a composite system inserter with other mounted electronic components is connected. Do a kid test. In this in-circuit test, each mounted flat package type IC element 1 or a composite system with other mounted electronic components is tested and evaluated. It is also possible to detect a soldering defect in a predetermined lead la of the flat package type IC cable 1 that the terminals 3a are in contact with. That is, since the contact pressure of the in-circuit probe pin against the lead 1a is relatively small, 20 to 50 gr, it is easy to detect when the lead 1a is in a non-conducting state due to poor soldering (lead lf failure). be done.
なお、上記においては、実装した電子部品が、二方向リ
ード端子付フラットパッケージ型IC素子の場合を示し
たが、この電子部品は例えば、四方向リード端子付フラ
ットパッケージ型IC素子等信の、リード付表面実装型
のものでもよい。In the above, the case where the mounted electronic component is a flat package type IC element with two-way lead terminals is shown, but this electronic component may be, for example, a flat package type IC element with four-way lead terminals, etc. A surface-mounted type may also be used.
また、前記実装されたフラットパッケージ型電子部品の
リード部に、対接させるプローブピンの先端面は、前記
リードの形状に合せた形状乃至構造にして置くことが、
位置決めのしやすさから望ましいが、必ずしも拘らない
。しかして、前記リード部に、対接させるプローブピン
に加える圧接力(圧力)は20〜50g「に常に設定す
る。つまり、所要のインサーキッドテストを行い得るに
充分な、電気的な接続がなされる程度に、対接させなが
ら一方では、リード部に変形(半田付部乃至パッドに対
する強制的な圧接)など起さない程度に対接させる。換
言すると、実装されているフラットパッケージ型電子部
品及びその電子部品のリード部に、実質的にはほとんど
荷重が加わらない程度で対接させる。上記により、前記
所要のインサーキッドテストを行い得るとともに、リー
ド部がパッドから浮いている場合も容品に検出されるこ
とになる。Further, the tip surface of the probe pin that is brought into contact with the lead portion of the mounted flat package electronic component may be shaped or structured to match the shape of the lead.
This is desirable for ease of positioning, but is not necessarily required. Therefore, the contact force (pressure) applied to the probe pin that is brought into contact with the lead section is always set at 20 to 50 g.In other words, sufficient electrical connection is made to perform the required in-circuit test. On the other hand, the lead portions are brought into contact with each other to the extent that they do not cause deformation (forcible pressure contact with soldering portions or pads).In other words, the mounted flat package type electronic components and The lead part of the electronic component is brought into contact with the electronic component to the extent that virtually no load is applied.The above method allows the required in-circuit test to be performed, and even if the lead part is floating from the pad, the product is not damaged. It will be detected.
[発明の効果]
上記、実施例から分るように、本発明のインサーキッド
テスト法は、繁雑な操作や熟練等要せずに、簡易にかつ
、正確に所要のテストをなしつる。[Effects of the Invention] As can be seen from the above examples, the in-circuit test method of the present invention allows required tests to be easily and accurately performed without requiring complicated operations or skill.
しかして、本発明法は、前記インサーキッドテストと併
せて、実装された電子部品のリードの浮き(半田付不良
)等の検出も出来る。また、上記の様にインサーキット
用パッドを設けずに、所要のインサーキッドテストを行
い得ることは、前記電子部品を実装する回路基板に就い
て、層構成の抜雑化ニヨるコストアップや設計費用のア
−:/ フ抑制ともなり、実用上条(の利点をもたらす
ものと言える。Therefore, in addition to the above-mentioned incircuit test, the method of the present invention can also detect loose leads (soldering defects) of mounted electronic components. In addition, being able to perform the required in-circuit test without providing in-circuit pads as described above means that the circuit board on which the electronic components are mounted will have to have a sloppy layer structure, which can lead to increased costs and design. It can also be said to reduce costs and bring about practical advantages.
第1図及び第2図は本発明のインサーキッドテスト法を
説明するためのもので、第1図は印刷回路基板上に実装
されたフラットパッケージ型IC素子のリード部にプロ
ーブピン先端面を対接させた状態を側面的に示す説明図
、第2図は第1図におけるフラットパッケージ型IC素
子のリード部にプローブピン先端面を対接させた状態を
拡大し斜視的に示す説明図である。
1・・・表面実装型電子部品
1a・・・表面実装型電子部品のリード部2・・・印刷
回路基板
3・・・プローブピン
3a・・・プローブピン先端面
4・・・パッド
5・・・半田Figures 1 and 2 are for explaining the in-circuit test method of the present invention, and Figure 1 shows the probe pin end face attached to the lead part of a flat package type IC element mounted on a printed circuit board. FIG. 2 is an explanatory diagram showing a side view of the state in which the probe pins are brought into contact with each other; FIG. . 1...Surface mount type electronic component 1a...Lead portion of surface mount type electronic component 2...Printed circuit board 3...Probe pin 3a...Probe pin tip surface 4...Pad 5... ·solder
Claims (1)
実装回路基板のインサーキッドテストにおいて、前記搭
載、実装された表面実装型電子部品のリード部に、プロ
ーブピン先端面を 20〜50grの圧力で対接させてインサーキッドテス
トを行うことを特徴とする実装回路基板のインサーキッ
ドテスト法。[Claims] In an in-circuit test of a mounted circuit board on which a required surface-mounted electronic component is mounted and mounted, the tip of a probe pin is attached to the lead portion of the mounted and mounted surface-mounted electronic component. An incircuit test method for a mounted circuit board, characterized in that an incircuit test is performed by bringing the surfaces into contact with each other under a pressure of 20 to 50 gr.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235655A JPH0282173A (en) | 1988-09-20 | 1988-09-20 | In-circuit testing method for package circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235655A JPH0282173A (en) | 1988-09-20 | 1988-09-20 | In-circuit testing method for package circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0282173A true JPH0282173A (en) | 1990-03-22 |
Family
ID=16989233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63235655A Pending JPH0282173A (en) | 1988-09-20 | 1988-09-20 | In-circuit testing method for package circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0282173A (en) |
-
1988
- 1988-09-20 JP JP63235655A patent/JPH0282173A/en active Pending
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